CMX972 Datasheet, PDF (19/41 Pages) CML Microcircuits – Small 32-lead VQFN Package

Quadrature Demodulator with IF PLL/VCO
CMX972
The PLL block has to be enabled from the General Control Register $1B, b2 (section 6.2.1) and the PLL R
Divider Register $2C, b7 (section 6.7.1), i.e. an AND function is performed on these two bits.
General Control
Register $1B, b2
0
0
1
1
PLL R Divider
Register $2C, b7
0
1
0
1
Table 14 PLL Control
PLL Enable
No
No
No
Yes
The PLL provides a lock detect function which can be read via C-BUS register $DC bit 6, see section
6.6.2. Register $2C provides the facility for the PLL charge pump to be placed in a high-impedance state,
this mode can be used, for example, to allow pre-steering of the VCO.
When using the CMX972 PLL, spurious products (spurs) in the receiver I/Q output may be observed. The
level of the spurs varies and is typically different in I and Q channels. The frequency of the spurs is linked
to the PLL M divider value, thus the comparison frequency and which of the divider modes (divide-by-2 or -
4) is selected for the receiver LO circuits. Operation in divide-by-2 mode is most predictable: all even
division ratios are problem free and all odd division ratios will give a spurious product at:
f_spur = f_lo / ( M * 2 )
In divide-by-4 mode odd divisions will produce a spur although at some low frequencies (e.g circa
100MHz) spur levels are much lower. At circa 300 MHz and above, even divisions are also problematic (in
divide-by-4 mode).
It is recommended that for safe operation of the CMX972 PLL, receiver LO divide-by-2 with even division
ratios, should be used.
5.3.2.2 VCO
The CMX972 VCO is a reflection oscillator that requires an external resonator circuit (see section 4.4) with
the negative resistance (NR) generator on the device. The VCO Control Register ($2F, section 6.8.1)
provides a control of the magnitude of the negative transconductance for optimum phase noise
performance. The NR minimum mode should be used with the low Q external tank circuit and NR
maximum with the higher Q circuits. For further information see section 7.7.
 2015 CML Microsystems Plc
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