CMX972 Datasheet, PDF (22/41 Pages) CML Microcircuits – Small 32-lead VQFN Package

Quadrature Demodulator with IF PLL/VCO
6.2 General Control Register
6.2.1 General Control Register - $1B: 8-bit write
This register controls general features such as powersave.
All bits of this register are cleared to ‘0’ during a General Reset command.
Bit:
7
RXDIV
6
5
4
3
2
1
0
DIFAMP
ENBIAS
VCOEN
PLLEN
RXEN
CMX972
0
0
General Control Register b7
Writing b7 = ’1’ the receiver LO is divided by 2; writing b7 = ’0’ the LO is divided by 4.
General Control Register b6
Reserved, set to ‘0’.
General Control Register b5 - b1
These bits control power up/power down of the various blocks of the IC.
In all cases ‘1’ = power up, ‘0’ = power down.
b5
Enable differential amplifiers (see also section 6.4.1)
b4
Enable bias
b3
Enable VCO (this bit also disables the RXLO input)
b2
PLL enable (see Table 14 and section 6.6.1)
Note: To enable the PLL b7 of the PLL M-Divider Register ($2C)
also needs to be set.
b1
Enable quadrature demodulator
Note: b1-b3 also control local oscillator signal routing, see section 5.3 and Table 13.
General Control Register b0
Reserved, set to ‘0’.
6.2.2 General Control Register - $EB: 8-bit read
This register reads the value in register $1B, see section 6.2.1 for details of bit functions.
6.3 Rx Control Register
6.3.1 Rx Control Register - $1C: 8-bit write
This register controls operational modes of the receiver such as gain setting.
All bits of this register are cleared to ‘0’ by a General Reset command.
Bit:
7
6
5
4
3
2
1
OUTDRV
COR
0
VGB2
VGB1
VGB0
VGA1
0
VGA0
 2015 CML Microsystems Plc
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