CS4239 Datasheet, PDF (9/98 Pages) Cirrus Logic – CrystalClear™ Portable ISA Audio System

CS4239
CrystalClear^TM Portable ISA Audio System
TIMING PARAMETERS (Continued)
Parallel Bus Timing
Parameter
Symbol
Min
Max
Units
IOW or IOR strobe width
t_STW
90
Data valid to IOW rising edge
(write cycle) tWDSU
22
IOR falling edge to data valid (read cycle)
tRDDV
SA <> and AEN setup to IOR or IOW falling edge
tADSU
22
SA <> and AEN hold from IOW or IOR rising edge
tADHD
10
DACK<> inactive to IOW or IOR falling edge (DMA cycle
t_SUDK1
60
immediately followed by a non-DMA cycle)
(Note 8)
DACK<> active from IOW or IOR rising edge (non-DMA
tSUDK2
0
cycle completion followed by DMA cycle)
(Note 8)
DACK<> setup to IOR falling edge (DMA cycles)
t_DKSUa
25
DACK<> setup to IOW falling edge
(Note 8) tDKSUb
25
Data hold from IOW rising edge
tDHD2
15
DRQ<> hold from IOW or IOR falling edge DTM(I10) = 0 tDRHD
(assumes no more DMA cycles needed)
DTM(I10) = 1
-25
ns
ns
60
ns
ns
ns
ns
ns
ns
ns
ns
45
ns
Time between rising edge of IOW or IOR to next falling
t_BWDN
80
ns
edge of IOW or IOR
Data hold from IOR rising edge
tDHD1
0
25
ns
DACK<> hold from IOW rising edge
DACK<> hold from IOR rising edge
tDKHDa
25
ns
t_DKHDb
25
ns
RESDRV pulse width high
Initialization Time
EEPROM Read Time
(Note 1) tRESDRV
1
(Note 1, 9) tINIT
3
(Note 1, 10) tEEPROM
1
ms
10
ms
190
ms
XTAL, 16.9344 MHz, frequency
(Notes 1, 11)
16.92
16.95
MHz
XTALI high time
(Notes 1, 11)
24
ns
XTALI low time
(Notes 1, 11)
24
ns
Sample Frequency
(Note 1) Fs
3.918
50
kHz
CS4610 DSP Serial Port Timing
SCLK rising to SDOUT valid
(Note 1) tPD1
60
ns
SCLK rising to FSYNC transition
(Note 1) tPD2
-20
20
ns
SDIN valid to SCLK falling
(Note 1) t_S1
30
ns
SDIN hold after SCLK falling
(Note 1) t_H1
30
ns
Notes: 8. AEN must be high during DMA cycles.
9. Initialization time depends on the power supply circuitry, as well as the the type of clock used.
10. EEPROM read time is dependent on amount of data in EEPROM. Minimum time relates to no
EEPROM present. Maximum time relates to EEPROM data size of 1k bytes.
11. The Sample frequency specification must not be exceeded.
DS253PP2
9