CS4239 Datasheet, PDF (7/98 Pages) Cirrus Logic – CrystalClear™ Portable ISA Audio System

CS4239
CrystalClear^TM Portable ISA Audio System
ADC1/DAC1 DIGITAL FILTER CHARACTERISTICS (Note 1)
Parameter
Symbol Min
Typ
Passband
Frequency Response
Passband Ripple
Transition Band
Stop Band
Stop Band Rejection
Group Delay
Group Delay Variation vs. Frequency
(0-0.40xFs)
8- and 16-bit formats
ADC1
DAC1
0
-1.0
0.40xFs
0.60xFs
74
Max
0.40xFs
+0.5
±0.1
0.60xFs
10/Fs
0.0
0.1/Fs
Units
Hz
dB
dB
Hz
Hz
dB
s
µs
µs
Timing Parameters (T_A = 25 °C; VA, VD1, VDF1-VDF3 = +5 V; outputs loaded with 30 pF;
Input Levels: Logic 0 = 0 V, Logic 1 = VD1, Rise/Fall time = 2 ns; Input/Output reference levels = 2.5 V)
Parameter
E²PROM Timing (Note 1)
Symbol
Min
Max
Units
SCL Low to SDA Data Out Valid
tAA
0
3.5
µs
Start Condition Hold Time
t_HD:STA
4.0
µs
Clock Low Period
tLSCL
4.7
µs
Clock High Period
t_HSCL
4.0
µs
Start Condition Setup Time
(for a Repeated Start Condition)
tSU:STA
4.7
µs
Data In Hold Time
t_HD:DAT
0
µs
Data In Setup Time
tSU:DAT
250
ns
SDA and SCL Rise Time
(Note 7) tR
1
µs
SDA and SCL Fall Time
t_F
300
ns
Stop Condition Setup Time
tSU:STO
4.7
µs
Data Out Hold Time
ZVPORT Timing
tDH
0
ns
ZLRCK delay after ZSCLK rising (to be ignored)
t_slrd
2
ns
ZLRCK setup before ZSCLK rising
tslrs
32
ns
ZSCLK low period
tsclkl
22
ns
ZSCLK high period
tsclkh
22
ns
ZSDATA setup to ZSCLK rising
tsdlrs
32
ns
ZSDATA hold after ZSCLK rising
t_sdh
2
ns
Notes 7. Rise time on SDA is determined by the capacitance of the SDA line with all connected gates and the
external pullup resistor required.
DS253PP2
7