CS4239 Datasheet, PDF (75/98 Pages) Cirrus Logic – CrystalClear™ Portable ISA Audio System

CS4239
CrystalClear^TM Portable ISA Audio System
When using an external CMOS clock, the
XTALO pin must be left floating with no trace
or external connection of any kind.
General Purpose Output Pins
Two general purpose outputs are provided to en-
able control of external circuitry (i.e. mute
function). XCTL1 and XCTL0 in the WSS
Codec register I10 are output directly to the ap-
propriate pin when enabled.
Pin XCTL1/ACDCS/DOWN is initially control-
led by the VCEN bit in the Hardware
Configuration data. If VCEN is zero, this pin be-
comes XCTL1 if the SDOUT pin is sampled
high during a high-to-low transition of RESDRV.
This pin can also output ACDCS if the SDOUT
pin is sampled low during a high-to-low transi-
tion of the RESDRV pin. SDOUT has an internal
pullup resistor. VCEN has the highest prece-
dence and will cause this pin to convert to the
DOWN function whenever VCEN is set.
Reset and Power Down
A RESDRV pin places the part into maximum
power conservation mode. When RESDRV goes
high, the PnP registers are reset - all logical de-
vices are disabled, all analog outputs are muted,
and the voltage reference then slowly decays to
ground. When RESDRV is brought low, an in-
itialization procedure begins which causes a full
calibration cycle to occur. When initialization is
completed, the registers will contain their reset
value and the part will be isolated from the bus.
RESDRV is required whenever the part is pow-
ered up. The initialization time varies based on
whether an E²PROM is present or not and the
size of the data in the E²PROM. After RESDRV
goes low, the part should not be written to for
approximately 200 ms to guarantee that the part
is ready to respond to commands. The exact tim-
ing is specified in the Timing Section in the front
of this data sheet.
DS253PP2
Software low-power states are available through
bits in the Control or WSS logical device regis-
ter space. See the CONTROL INTERFACE
section for more information.
Address Port Configuration
The part provides a method for motherboards to
hide the part from standard PnP (or traditional
Crystal Key) software. BIOSes can use this
method to set the part at a unique address, and
report the device as a System Dev. Node to the
operating system.
On the high to low transition of the RESDRV
pin, the part samples the state of the APSEL and
SCL, which have internal 100 kΩ pullups to
+5 V. APSEL selects the Address Port used to
configure the part. When APSEL is left high, the
Address Port is 0x279 and backwards compat-
ible to previous chips and standard PnP software.
When APSEL is externally tied to SGND, the
Address Port is moved to one of two locations,
selected by a strapping option on the SCL pin. If
SCL is sampled high (default), then the Address
Port is moved to 0x308. If SCL is strapped low
with an external 10 kΩ resistor to SGND, the
Address Port is moved to 0x388.
If the Address Port is moved (APSEL = 0) then
the device is no longer PnP compliant; however,
it will still respond to all the standard PnP com-
mands using the new Address Port. In addition,
the new Address Port supports the traditional
Crystal Key or the new Crystal Key 2.
Multiplexed Pin Configuration
On the high to low transition of the RESDRV
pin, the part samples the state of the MCLK and
SDOUT which have internal 100 kΩ pullups to
+5 V.
The state of MCLK at the time RESDRV is
brought low determines the function of the
CDROM interface pins. If MCLK is sampled
high, then CDCS, CDACK, CDINT, CDRQ are
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