CS4239 Datasheet, PDF (41/98 Pages) Cirrus Logic – CrystalClear™ Portable ISA Audio System

CS4239
CrystalClear^TM Portable ISA Audio System
TEST
Factory Test. These bits are used for
factory testing and must remain at 0
for normal operation.
Left DAC2 Volume (I18)
Default = 00000111
D7 D6 D5 D4 D3 D2 D1 D0
LD2OM LD2IM rbc LD2A4 LD2A3 LD2A2 LD2A1 LD2A0
Note: When AUX1R in X18 is set, this register also
controls the volume for the LAUX1 analog input. See
I2 description for volume description of LAUX1.
LD2A4-LD2A0 Left DAC2 Attenuation. The least sig-
nificant bit represents 1.5 dB, with
01000 = 0 dB. The total range is
+12 dB to -33.0 dB with
11111 = muted. See Table 8.
LD2IM
Left DAC2 Input Mute. When set,
the left DAC2 to the input mixer is
muted.
LD2OM
Left DAC2 Output Mute. When set,
the left DAC2 to the output mixer is
muted.
Right DAC2 Volume (I19)
Default = 11000111
D7 D6 D5 D4 D3 D2 D1 D0
RD2OM RD2IM rbc RD2A4 RD2A3 RD2A2 RD2A1 RD2A0
Note: When AUX1R in X18 is set, this register also
controls the volume for the RAUX1 analog input. See
I3 description for volume description of RAUX1.
RD2A4-RD2A0 Right DAC2 Attenuation. The least
significant bit represents 1.5 dB, with
01000 = 0 dB. The total range is
+12 dB to -33.0 dB with
11111 = muted. See Table 8.
RD2IM
Right DAC2 Input Mute. When set,
the Right DAC2 to the input mixer is
muted.
RD2OM
Right DAC2 Output Mute. When set,
the right DAC2 to the output mixer is
muted.
Control/RAM Access (I20)
Default = xxxxxxxx
D7 D6 D5 D4 D3 D2 D1 D0
CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0
This register is identical to CTRLbase+5. For back-
wards compatibility, this register is not enabled until
PAE in X18 is set. When PAE is clear, this register is
read/writable, but does nothing.
CR7-CR0
This register controls the loading of
the part’s internal RAM as well as in-
ternal processor commands. See the
Hostload Procedure section as well
as CTRLbase+5 register description
for more details.
RAM Access End (I21)
Default = xxxxxxxx
D7 D6 D5 D4 D3 D2 D1 D0
RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0
This register is identical to CTRLbase+6. For back-
wards compatibility, this register is not enabled until
PAE in X18 is set. When PAE is clear, this register is
read/writable, but does nothing.
RE7-RE0
A 0 written to this location resets the
previous location, I20, from data
download mode, to command mode.
Alternate Sample Frequency Select (I22)
Default = 00000000
D7 D6 D5 D4 D3 D2 D1 D0
SRE DIV5 DIV4 DIV3 DIV2 DIV1 DIV0 CS2
CS2
Clock 2 Base Select. This bit selects
the base clock frequency used for
generating the audio sample rate.
Note that the part uses only one
crystal to generate both clock base
frequencies. This bit can be disabled
by setting IFSE in X11.
0 - 24.576 MHz base
1 - 16.9344 MHz base
DS253PP2
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