CS4239 Datasheet, PDF (77/98 Pages) Cirrus Logic – CrystalClear™ Portable ISA Audio System

CS4239
CrystalClear^TM Portable ISA Audio System
Microphone Level Input
The microphone level input, MIC, include a se-
lectable -22.5 dB to +22.5 dB gain stage for
interfacing to an external microphone. An addi-
tional 20 dB gain block is also available. The
20 dB gain block can be switched off to provide
another mono line-level input. Figure 21 illus-
trates a single-ended microphone input buffer
circuit that will support lower gain mics. The cir-
cuit in Figure 21 supports dynamic mics and
phantom-powered mics that use the ring portion
of the jack for power.
2 kΩ
47 kΩ
0.1 µF
47 kΩ
+
1 µF
MC33078 or
MC33178
0.33 µF
4.7 kΩ ^X7R
VREF
MIC
600 Ω
+
2.7 nF
NPO
10 µF
Figure 21. Microphone Input
Mono Input
The mono input, MIN, is useful for mixing the
output of the "beeper" (timer chip), provided in
all PCs, with the rest of the audio signals. The
MIN pin can be mixed into the output mixer
with at a 0 or -9 dB level. Also, the MIM and
MIMR bits support muting the input to the left
and right channels respectively. Figure 22 illus-
trates a typical input circuit for the Mono In. If
MIN is driven from a CMOS gate, the 4.7 kΩ
should be tied to AGND instead of VA+. Al-
though this input is described for a low-quality
beeper, the input is of the same high-quality as
all other analog inputs and may be used for other
purposes.
+5VA (Low Noise) or
AGND - if CMOS Source
4.7 kΩ
1 47 kΩ
MIN
0.1 µF
2.7 nF
Figure 22. Mono Input
Line Level Outputs
The analog output section provides a stereo line-
level output. The other output types (headphone
and speaker) can be implemented with external
circuitry. LOUT and ROUT outputs should be
capacitively coupled to external circuitry. Both
LOUT and ROUT need 1000 pF NPO capacitors
between the pin and AGND.
Miscellaneous Analog Signals
The VREF pin is typically 2.2 V and provides a
common mode signal for single-supply external
circuits. VREF only supports light DC loads and
should be buffered if AC loading is needed. For
typical use, a 0.1 µF in parallel with a 10 µF ca-
pacitor should be connected to VREF.
GROUNDING AND LAYOUT
Figure 23 is a suggested layout for motherboard
designs and Figure 24 is a suggested layout for
add-inn cards. For optimum noise performance,
the device should be located across a split ana-
log/digital ground plane. The digital ground
plane should extend across the ISA bus pins as
well as the internal digital interface pins.
DGND1 is ground for the data bus and should
be electrically connected to the digital ground
plane which will minimize the effects of the bus
interface due to transient currents during bus
switching. SGND1-4 should also be connected to
the digital ground plane to minimize coupling
into the analog section. Figure 25 shows the rec-
ommended positioning of the decoupling
capacitors. The capacitors must be on the same
layer as, and close to, the part. The vias shown
DS253PP2
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