CS4239 Datasheet, PDF (38/98 Pages) Cirrus Logic – CrystalClear™ Portable ISA Audio System

CEN
SDC
CAL1,0
PPIO
CPIO
38
CS4239
CrystalClear^TM Portable ISA Audio System
Capture Enabled. This bit enables the
capture of data. The WSS Codec
will generate a DRQ and respond to
DACK signal when CEN is enabled
and CPIO=0. If CPIO=1, CEN en-
ables PIO capture mode. CEN may
be set and reset without setting the
MCE bit.
0 - Capture Disabled (capture DRQ
and PIO inactive)
1 - Capture Enabled
Single DMA Channel: This bit will
force BOTH capture and playback
DMA requests to occur on the Play-
back DMA channel. This bit forces
the WSS Codec to use one DMA
channel. Should both capture and
playback be enabled in this mode,
only the playback will occur. See the
DMA Interface section for further ex-
planation.
0 - Dual DMA channel mode
1 - Single DMA channel mode
Calibration: These bits determine
which type of calibration the WSS
Codec performs whenever the Mode
Change Enable (MCE) bit, R0,
changes from 1 to 0. The number of
sample periods required for calibra-
tion is listed in parenthesis.
0 - No calibration (0)
1 - Converter calibration (321)
2 - DAC calibration (120)
3 - Full calibration (450)
Playback PIO Enable: This bit deter-
mines whether the playback data is
transferred via DMA or PIO.
0 - DMA transfers
1 - PIO transfers
Capture PIO Enable: This bit deter-
mines whether the capture data is
transferred via DMA or PIO.
0 - DMA transfers
1 - PIO transfers
Caution: This register, except bits CEN and
PEN, can only be written while in Mode Change
Enable (either MCE or PMCE). See the Chang-
ing Sampling Rate section for more details.
Pin Control (I10)
Default = 0000000x
D7 D6 D5 D4 D3 D2 D1 D0
XCTL1 XCTL0 OSM1 OSM0 DEN DTM IEN res
IEN
Interrupt Enable: This bit enables the
interrupt pin. The Interrupt pin will re-
flect the value of the INT bit of the
Status register (R2). The interrupt
pin is active high.
0 - Interrupt disabled
1 - Interrupt enabled
DTM
DMA Timing Mode. MODE 2 & 3 only.
When set, causes the current DMA
request signal to be deasserted on
the rising edge of the IOW or IOR
strobe during the next to last byte of
a DMA transfer. When DTM = 0 the
DMA request is released on the fall-
ing edge of the IOW or IOR during
the last byte of a DMA transfer.
DEN
Dither Enable: When set, triangular
pdf dither is added before truncating
the ADC 16-bit value to 8-bit, un-
signed data. Dither is only active in
the 8-bit unsigned data mode.
0 - Dither enabled
1 - Dither disabled
OSM1-OSM0
These bits are enabled by setting
SRE = 1 in I22. These bits in com-
bination with DIV5-DIV0 and CS2
(I22) determine the current sample
rate of the WSS Codec when
SRE = 1. Note that these bits can
be disabled by setting IFSE in X11.
00 - 12 kHz < Fs ≤ 24 kHz
01 - Fs > 24 kHz
10 - Fs ≤ 12 kHz
11 - reserved
DS253PP2