CS4239 Datasheet, PDF (24/98 Pages) Cirrus Logic – CrystalClear™ Portable ISA Audio System

CS4239
CrystalClear^TM Portable ISA Audio System
HW Config. Byte 10: FM Volume Scaling,
Default = 00100000
D7 D6 D5 D4 D3 D2 D1 D0
res FMS2 FMS1 FMS0 res res res res
FMS2-FMS0
FM Volume Scaling relative to wave-
table digital input. These bits set the
default FM volume level relative to
the CS9236 wavetable interface
port. Once initialized, these bits can
be controlled through X19. These
bits are provided for backwards com-
patibility with previous chips.
010 - 0 dB
011 - +6 dB
100 - -12 dB
101 - -6 dB
110 - +12 dB
111 - +18 dB
HW Config. Byte 14: Mono & DSP Port
Control, Default = 10000000
D7 D6 D5 D4 D3 D2 D1 D0
MIM res res res SF1 SF0 SPE MIA
This register sets the power up defaults for these fea-
tures. After power-up, I16 may be used to control the
DSP serial port, and I26 may be used to control the
Mono Input.
MIA
Mono Input Attenuate. When set, the
MIN input is attenuated 9 dB. When
clear, the MIN volume is 0 dB.
SPE
DSP Serial Port Enable. When set,
the DSP serial port is enabled.
SF1,0
DSP Serial Port Format. Selects the
format of the serial port once en-
abled by SPE. See the DSP Serial
Audio Data Port section for more de-
tails.
00 - 64-bit enhanced.
01 - 64-bit.
10 - 32 bit.
11 - ADC/DAC.
MIM
Mono In mute. When set, the MIN
analog input is muted. When clear,
MIN is mixed into the output mixer
at a level set by MIA.
HW Config. Byte 15: E²PROM Checksum
Default = xxxxxxxx
D7 D6 D5 D4 D3 D2 D1 D0
EC7 EC6 EC5 EC4 EC3 EC2 EC1 EC0
EC7-EC0
E²PROM checksum byte. Starts with
the first byte of the size (after
55h/BBh) and ends with the last pro-
grammed byte of the E²PROM. Only
valid if EECS in Hardware Configura-
tion Byte 16 is set.
HW Config. Byte 16: Global Config. Byte 2
Default = 00000000
D7 D6 D5 D4 D3 D2 D1 D0
res EECS AUX1R 3DEN DSPD1 PSH ZVEN res
This register sets the power up defaults for these fea-
tures. After power-up, X18 may be used to control all
bits except EECS.
ZVEN
ZVPORT Enable. When set, the
ZVPORT pins are enabled and se-
lected as input to DAC2. While the
ZVPORT is enabled, no other input
to DAC2 is allowed (synthesizers or
DSP).
PSH
Playback Sample Hold. When set, the
last sample is held in DAC1 when
PEN is cleared. When clear, zero is
sent to DAC1 when PEN is cleared.
DSPD1
DSP port controls DAC1. When set,
the serial DSP port controls DAC1 in-
stead of the ISA playback FIFO.
3DEN
3D Sound Enable. When set, 3D
sound is enabled on L/ROUT.
AUX1R
AUX1 Remap. When set, writes to
I18/19 (DAC2 volume) also control
the AUX1 volume. When clear,
I18/19 control DAC2 volume and
I2/3 control AUX1 volume. This bit
provides some backwards compatibil-
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DS253PP2