CS4239 Datasheet, PDF (28/98 Pages) Cirrus Logic – CrystalClear™ Portable ISA Audio System

CS4239
CrystalClear^TM Portable ISA Audio System
The WSS functions include stereo Analog-to-
Digital and Digital-to-Analog converters (ADCs
and DACs), analog mixing, anti-aliasing and re-
construction filters, line and microphone level
inputs, simultaneous capture and playback (at in-
dependent sample frequencies) and a parallel bus
interface.
Enhanced Functions (MODEs)
The initial state is labeled MODE 1 and forces
the part to appear as a CS4248. The more popu-
lar second mode, MODE 2, forces the part to
appear as a CS4231 super set and is compatible
with the CS4232. To switch from MODE 1 to
MODE 2, the CMS1,0 bits, in the MODE and
ID register (I12), should be set to 10 respec-
tively. When MODE 2 is selected, the bit IA4 in
the Index Address register (R0) will be decoded
as a valid index pointer providing 16 additional
registers and increased functionality over the
CS4248.
To reverse the procedure, set the CMS1,0 bits to
00 and the part will resume operation in
MODE 1. Except for the Capture Data Format
(I28), Capture Base Count (I30/31), and Alter-
nate Feature Status (I24) registers, all other
Mode 2 functions retain their values when re-
turning to Mode 1.
MODE 3 is selected by setting CMS1,0 to 11.
MODE 3 allows access to a third set of "ex-
tended registers" which are designated X0-X31.
The extended registers are accessed through I23.
The additional MODE 3 functions are:
1. A full symmetrical mixer. This changes the in-
put multiplexer to a input mixer.
2. Independent sample frequency control on the
ADCs and DACs.
3. Programmable Gain and Attenuation on the
Microphone inputs.
FIFOs
The WSS Codec contains 16-sample FIFOs in
both the playback and capture digital audio data
paths. The FIFOs are transparent and have no
programming associated with them.
When playback is enabled, the playback FIFO
continually requests data until the FIFO is full,
and then makes requests as positions inside the
FIFO are emptied, thereby keeping the playback
FIFO as full as possible. Thus when the system
cannot respond within a sample period, the FIFO
starts to empty, avoiding a momentary loss of
audio data. If the FIFO runs out of data, the last
valid sample can be continuously output to the
DACs (if DACZ in I16 is clear) which will
eliminate pops from occurring.
When capture is enabled, the capture FIFO tries
to continually stay empty by making requests
every sample period. Thus when the system can-
not respond within a sample period, the capture
FIFO starts filling, thereby avoiding a loss of
data in the audio data stream.
WSS Codec PIO Register Interface
Four I/O mapped locations are available for ac-
cessing the Codec functions and mixer. The
control registers allow access to status, audio
data, and all indirect registers via the index reg-
isters. The IOR and IOW signals are used to
define the read and write cycles respectively. A
PIO access to the Codec begins when the host
puts an address on to the ISA bus which matches
WSSbase and drives AEN low. WSSbase is pro-
grammed during a Plug and Play configuration
sequence. Once a valid base address has been
decoded then the assertion of IOR will cause the
WSS Codec to drive data on the ISA data bus
lines. Write cycles require the host to assert data
on the ISA data bus lines and strobe the IOW
signal. The WSS Codec will latch data into the
PIO register on the rising edge of the IOW
strobe.
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