CS4239 Datasheet, PDF (73/98 Pages) Cirrus Logic – CrystalClear™ Portable ISA Audio System

CS4239
CrystalClear^TM Portable ISA Audio System
PLAYBACK DMA REGISTERS
The playback DMA registers (I14/15) are used
for sending playback data to the DACs in
MODE 2 and 3. In MODE 1, these registers
(I14/15) are used for both playback and capture;
therefore, full-duplex DMA operation is not pos-
sible.
When the playback Current Count register rolls
under, the Playback Interrupt bit, PI, (I24) is set
causing the INT bit (R2) to be set. The interrupt
is cleared by a write of any value to the Status
register (R2), or writing a "0" to the Playback
Interrupt bit, PI (I24).
CAPTURE DMA REGISTERS
The Capture DMA Base registers (I30/31) pro-
vide a second pair of Base registers that allow
full-duplex DMA operation. With full-duplex op-
eration capture and playback can occur
simultaneously. These registers are provided in
MODE 2 and 3 only.
When the capture Current Count register rolls
under, the Capture Interrupt bit, CI, (I24) is set
causing the INT bit (R2) to be set. The interrupt
is cleared by a write of any value to the Status
register (R2), or writing a "0" to the Capture In-
terrupt bit, CI (I24).
WSS Codec Interrupt
The INT bit of the Status register (R2) always
reflects the status of the WSS Codec’s internal
interrupt state. A roll-over from any Current
Count register (DMA playback, DMA capture, or
Timer) sets the INT bit. This bit remains set until
cleared by a write of ANY value to Status regis-
ter (R2), or by clearing the appropriate bit or bits
(PI, CI) in the Alternate Feature Status register
(I24).
The Interrupt Enable (IEN) bit in the Pin Control
register (I10) determines whether the interrupt
assigned to the WSS Codec responds to the in-
DS253PP2
terrupt event. When the IEN bit is low, the inter-
rupt is masked and the IRQ pin assigned to the
WSS Codec is held low. However, the INT bit in
the Status register (R2) always responds to the
counter.
Error Conditions
Data overrun or underrun could occur if data is
not supplied to or read from the WSS Codec in
an appropriate amount of time. The amount of
time for such data transfers depends on the fre-
quency selected within the WSS Codec.
Should an overrun condition occur during data
capture, the last whole sample (before the over-
run condition) will be read by the DMA
interface. A sample will not be overwritten while
the DMA interface is in the process of transfer-
ring the sample.
Should an underrun condition occur in a play-
back case the last valid sample will be output
(assuming DACZ = 0) to the digital mixer. This
will mask short duration error conditions. When
the next complete sample arrives from the host
computer the data stream will resume on the
next sample clock.
The overrun and underrun error bits in the Alter-
nate Feature Status register, I24, are cleared by
first clearing the condition that caused the over-
run or underrun error, followed by writing the
particular bit to a zero. As an example, to clear
the playback underrun bit PU, first a sample
must be sent to the WSS Codec, and then the PU
bit must be written to a zero.
DIGITAL HARDWARE DESCRIPTION
The best example of hardware connection for the
different sections of this part is the Reference
Design Data Sheet. The Reference Design Data
Sheet contains all the schematics, layout plots
and a Bill of Materials; thereby providing a com-
plete example.
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