CS4239 Datasheet, PDF (31/98 Pages) Cirrus Logic – CrystalClear™ Portable ISA Audio System

CS4239
CrystalClear^TM Portable ISA Audio System
DIRECT MAPPED REGISTERS
The first two WSS Codec registers provide indi-
rect accessing to more codec registers via an
index register. The other two registers provide
status information and allow audio data to be
transferred to and from the WSS Codec without
using DMA cycles or indexing.
Note that register defaults are listed in binary
form with reserved bits marked with ’x’ to indi-
cate unknown. Bits in the default marked with
an ’e’ indicate that the bit is initialized through
E²PROM. To maintain compatibility with future
parts, these reserved bits must be written as 0,
and must be masked off when the register is
read. The current value read for reserved bits is
not guaranteed on future revisions. While the re-
served bits are listed as "res" in the bit position,
"rbc" is used for "reserved, backwards compat-
ible" for bits that were used on previous chips,
but are no longer required on this chip. These
bits are read/writable but should generally be set
to 0 for backwards compatibility.
Index Address Register
(WSSbase+0, R0)
D7 D6 D5 D4 D3 D2 D1 D0
INIT MCE TRD IA4 IA3 IA2 IA1 IA0
IA3-IA0
Index Address: These bits define the
address of the indirect register ac-
cessed by the Indexed Data register
(R1). These bits are read/write.
IA4
Allows access to indirect registers 16
- 31. In MODE 1, this bit is re-
served and must be written as zero.
TRD
Transfer Request Disable: This bit,
when set, causes DMA transfers to
cease when the INT bit of the Status
Register (R2) is set. Independent for
playback and capture interrupts.
0 - Transfers Enabled (playback and
capture DRQs occur uninhibited)
1 - Transfers Disabled (playback and
capture DRQ only occur if INT bit
is 0)
MCE
Mode Change Enable: This bit must
be set whenever the current mode
of the WSS Codec is changed. The
Data Format (I8, I28) and Interface
Configuration (I9) registers CANNOT
be changed unless this bit is set.
The exceptions are CEN and PEN
which can be changed "on-the-fly".
The DAC output is muted when
MCE is set.
INIT
WSS Codec Initialization: This bit is
read as 1 when the Codec is in a
state in which it cannot respond to
parallel interface cycles. This bit is
read-only.
Immediately after RESET (and once the WSS
Codec has left the INIT state), the state of this
register is: 010x0000 (binary - where ’x’ indi-
cates unknown).
During initialization and software power down
(PDWN in CTRLbase+7), this register cannot be
written and always reads 10000000 (80h)
Indexed Data Register
(WSSbase+1, R1)
D7 D6 D5 D4 D3 D2 D1 D0
ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
ID7-ID0
Indexed Data register: These bits are
the indirect register referenced by
the Indexed Address register (R0).
DS253PP2
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