CS4239 Datasheet, PDF (50/98 Pages) Cirrus Logic – CrystalClear™ Portable ISA Audio System

CS4239
CrystalClear^TM Portable ISA Audio System
LD1IM
Left DAC1 Input Mixer Mute.
When set to 1, the output from the
Left DAC1 is muted to the Left input
mixer. See Figure 4.
Independent ADC Fs (X12)
Default = xxxxxxxx
D7 D6 D5 D4 D3 D2 D1 D0
SRAD7 SRAD6 SRAD5 SRAD4 SRAD3 SRAD2 SRAD1 SRAD0
SRAD7-SRAD0 Sample Rate frequency select for
the A/D converter. See Table 10.
Independent DAC Fs (X13)
Default = xxxxxxxx
D7 D6 D5 D4 D3 D2 D1 D0
SRDA7 SRDA6 SRDA5 SRDA4 SRDA3 SRDA2 SRDA1 SRDA0
SRDA7-SRDA0 Sample Rate frequency select for
the D/A converter. See Table 10.
Reserved, backwards compatible (X14)
Default = xxxxxxxx
D7 D6 D5 D4 D3 D2 D1 D0
rbc rbc rbc rbc rbc rbc rbc rbc
rbc
Reserved, backwards compatible.
Reserved, backwards compatible (X15)
Default = xxxxxxxx
D7 D6 D5 D4 D3 D2 D1 D0
rbc
rbc rbc rbc rbc rbc rbc rbc
rbc
Reserved, backwards compatible.
Left Wavetable Serial Port Mute (X16)
Default = exxxxxx
D7 D6 D5 D4 D3 D2 D1 D0
LWM res rbc rbc rbc rbc rbc rbc
LWM
Left Wavetable Serial Port Mute.
When set, the Left Wavetable Serial
Input to DAC2 is muted. The default
state of this bit is the inverse of
WTEN in the Hardware Configura-
tion Data, Global Configuration byte.
Right Wavetable Serial Port Mute (X17)
Default = exxxxxxx
D7 D6 D5 D4 D3 D2 D1 D0
RWM res rbc
rbc
rbc
rbc
rbc
rbc
RWM
Right Wavetable Serial Port Mute.
When set, the Right Wavetable Se-
rial Input to DAC2 is muted. The
default state of this bit is the inverse
of WTEN in the Hardware Configura-
tion Data, Global Configuration byte.
3D and RAM Port Enable (X18)
Default = 0xeeeee0
D7 D6 D5 D4 D3 D2 D1 D0
PAE res AUX1R 3DEN DSPD1 PSH ZVEN DLEN
DLEN
Digital Loopback Enable. When set,
the input to DAC1 to comes from the
ADCs. While DLEN is on, no other
data is sent to DAC1. This provides
a test path that is generally not used
in normal operation.
ZVEN
ZVPORT Enable. When set, the
ZVPORT pins are enabled and se-
lected as input to DAC2. While the
ZVPORT is enabled, no other input
to DAC2 is allowed (synthesizers or
DSP).
PSH
Playback Sample Hold. When set, the
last sample is held in DAC1 when
PEN is cleared. When clear, zero is
sent to DAC1 when PEC is cleared.
DSPD1
DSP port controls DAC1. When set,
the serial DSP port controls DAC1 in-
stead of the ISA playback FIFO.
3DEN
3D Sound Enable. When set, 3D
sound is enabled on L/ROUT. This
bit is also controlled through C3.
AUX1R
AUX1 Remap. When set, writes to
I18/19 (DAC2 volume) also control
the AUX1 volume. When clear,
I18/19 control DAC2 volume and
I2/3 control AUX1 volume. This bit
provides some backwards compatibil-
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DS253PP2