AMC1210 Datasheet, PDF (9/47 Pages) Burr-Brown (TI) – Quad Digital Filter for 2nd-Order Delta-Sigma Modulator

AMC1210
www.ti.com
PARALLEL MODE 2
SBAS372A – APRIL 2006 – REVISED OCTOBER 2006
TIMING CHARACTERISTICS⁽¹⁾
Over recommended operating free-air temperature range at –40°C to +125°C, DVDD = +5V, BVDD = +2.7V, unless otherwise noted.
PARAMETER ⁽²⁾
t_w1
CS low width
t_w2
CS high width
t_d1
Delay time from ALE low to CS high
t_d2
Delay time from WR high to CS high
t_d3
Delay time from CS low to WR low
t_w3
WR low width
t_w4
WR high width
t_w5
ALE high width
t_d4
Delay time from ALE low to WR low
t_su1
Setup time from address valid to ALE low
t_h1
Hold time from ALE low to address invalid
t_d5
Delay time from CS low to RD low
t_su2
Setup time from data valid to WR high
t_h2
Hold time from WR high to data invalid
t_d6
Delay time from RD high to CS high
t_w6
RD low width
t_w7
RD high width
t_d7
Delay time from RD low to data valid
t_d8
Delay time from RD high to databus in tristate
t_d9
Delay time from ALE low to RD low
MIN
MAX
UNIT
40
ns
5
ns
5
ns
5
ns
3
ns
10
ns
10
ns
10
ns
10
ns
6
ns
5
ns
0
ns
6
ns
5
ns
6
ns
30
ns
13
ns
30
ns
0
10
ns
10
ns
(1) All input signals are specified with t_R = t_F = 5ns (10% to 90% of BVDD) and timed from a voltage level of (V_IL + V_IH)/2.
(2) t_w2 is obsolete if CS stays low between the WR, RD and ALE pulses.
Parallel mode 2, write access
CS
t_w1
WR
RD
ALE
AD(7:0)
Internal address
t_w5
t_su1
ADDR
Parallel mode 2, read access
CS
WR
RD
ALE
t_w2
t_d1
t_d2
t_d4
t_h1
ADDR
t_su2
MSB
t_d9
t_d6
AD(7:0)
Internal address
ADDR
ADDR
MSB
t_d3
t_w4
t_h2
LSB
t_d5
t_w7
t_d7
t_d8
LSB
t_w3
MSB
ADDR+1
t_w6
MSB
ADDR+1
Figure 5. Parallel Mode 2 Timing
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