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AMC1210 Datasheet, PDF (33/47 Pages) Burr-Brown (TI) – Quad Digital Filter for 2nd-Order Delta-Sigma Modulator | |||
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AMC1210
www.ti.com
SBAS372A â APRIL 2006 â REVISED OCTOBER 2006
Clock Divider Register (address 0x1B)
The Clock Divider Register sets up the signal generator, the modulator clock division and the signal generator
clock. Table 22 shows the Clock Divider Register.
Table 22. Clock Divider Register
Bit 15
â
Bit 14
â
Bit 13
â
Bit 12
HBE
Bit 11
MFE
Bit 10
SGE
Bit 9
PCAL
Bit 8
SCS1
Bit 7
SCS0
Bit 6
MD2
Bit 5
MD1
Bit 4
MD0
Bit 3
SD3
Bit 2
SD2
Bit 1
SD1
Bit 0
SD0
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
R
R
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
BIT POSITION
15â13
12
11
10
9
8â7
6â4
3â0
BIT
â
HBE
MFE
SGE
PCAL
SCS1âSCS0
MD2âMD0
SD3âSD0
DESCRIPTION
Unused. Always read '0'.
Signal Generator High-Current Output.
0: The high current option for pins PWM1 and PWM2 is disabled
1: The PWM1 and PWM2 outputs are in High Current Mode
Master Filter Enable. Functionally AND'ed with bit FEN in the Sinc Filter Parameter
Register.
0: Sinc filter units of all filter modules are disabled.
1: Sinc filter units can be enabled if bit FEN is '1'.
Signal Generator enable.
0: Signal generator is disabled
1: Signal generator is enabled
Start of phase correction.
Writing a '1' to this bit starts the phase calibration. Reading this bit shows the phase
calibration status:
1: The phase calibration is performing
0: No phase calibration is performing
Signal generator Control Select (necessary for Phase Calibration and Demodulation on the
selected channel).
00: The phase calibration is performed on filter module 1
01: The phase calibration is performed on filter module 2.
10: The phase calibration is performed on filter module 3.
11: The phase calibration is performed on filter module 4.
Modulator clock divider.
The coding is equal to the first eight codes in SD; see below.
Signal generator clock divider.
0000: Clock divider is off, outgoing clock equals incoming clock
0001: Outgoing clock is divided by 2
0010: Outgoing clock is divided by 3
0011: Outgoing clock is divided by 4
0100: Outgoing clock is divided by 5
0101: Outgoing clock is divided by 6
0110: Outgoing clock is divided by 7
0111: Outgoing clock is divided by 8
1000: Outgoing clock is divided by 9
1001: Outgoing clock is divided by 10
1010: Outgoing clock is divided by 11
1011: Outgoing clock is divided by 12
1100: Outgoing clock is divided by 13
1101: Outgoing clock is divided by 14
1110: Outgoing clock is divided by 15
1111: Outgoing clock is divided by 16
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