AMC1210 Datasheet, PDF (14/47 Pages) Burr-Brown (TI) – Quad Digital Filter for 2nd-Order Delta-Sigma Modulator

AMC1210
SBAS372A – APRIL 2006 – REVISED OCTOBER 2006
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During continuous read or write, the address increments after each read or write. When the address reaches
7Fh, the address counter starts over from 0. The data is written into the register map on the 16th WR of a data
word. If the CS is inactive before the 16th WR in a data word, the data is not written into the register map; the
data is lost. Figure 12 shows a typical example of this functionality.
CS
WR
RD
AD0
8 SPICLKs 8 SPICLKs 8 SPICLKs 8 SPICLKs 8 SPICLKs 8 SPICLKs 8 SPICLKs 8 SPICLKs 8 SPICLKs
Address 1st Data to write 2nd Data to write 3rd Data to write 4th Data to write
Don't care 1st read Data
2nd read Data
3rd read Data
4th read Data
Figure 12. Typical Serial Communication Operation
SPI Option 2
SPI option 2 is recommended for use when the clock speed is greater than 25MHz. The only difference between
option 1 and 2 is the edge from which the output data is strobed. In option 2, the user should read the data on
the rising edge after the data from the register map is latched (one half clock cycle after Option 1). In this case,
an extra clock cycle is needed (25 clock cycles instead of 24). See the timing diagram in Figure 3.
Parallel Mode 1
In Parallel Mode 1, the host port uses WR and RD for independent write and read access to the AMC1210. The
current cycle is processed only when the CS input of the AMC1210 is low. RD indicates to the AMC1210 that
the host processor has requested a data transfer. The AMC1210 then outputs data to the host.
To configure the registers in the AMC1210, the host process issues a WR signal to indicate that valid data is
available on the bus. The data is latched into the AMC1210 with the rising edge of the WR. The address for the
AMC1210 must be valid at the first rising edge of WR. To indicate that an address is issued, the signal ALE
must be set to high before the WR signal is set to low. The CS signal can stay low between two consecutive
writes or reads.
Figure 4 provides a detailed timing diagram of Parallel Mode 1.
Parallel Mode 2
In Parallel Mode 2, the host port uses WR and RD for independent write and read access to the AMC1210. The
current cycle is processed only when the CS input of the AMC1210 is low. RD indicates to the AMC1210 that
the host processor has requested a data transfer. The AMC1210 then outputs data to the host.
To configure the AMC1210 registers, the host process issues a WR signal to indicate that valid data is available
on the bus. With the rising edge of WR, the data is latched into the AMC1210. The address is latched into
AMC1210 when the signal ALE is set to low. The CS signal can stay low between two consecutive writes or
reads.
Figure 5 provides a detailed timing diagram of Parallel Mode 2.
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