AMC1210 Datasheet, PDF (28/47 Pages) Burr-Brown (TI) – Quad Digital Filter for 2nd-Order Delta-Sigma Modulator

AMC1210
SBAS372A – APRIL 2006 – REVISED OCTOBER 2006
www.ti.com
BIT POSITION
7
6
5
4
3
2
1
0
BIT
IFL4
IFH4
IFL3
IFH3
IFL2
IFH2
IFL1
IFH1
DESCRIPTION
Low-level interrupt flag for Filter 4
0: Comparator Filter 4 output is above the low limit threshold
1: Comparator Filter 4 output is equal to or below the low level threshold, if enabled
High-level interrupt flag for Filter 4
0: Comparator Filter 4 output is below the high limit threshold
1: Comparator Filter 4 output is equal to or above the high level threshold, if enabled
Low-level interrupt flag for Filter 3
0: Comparator Filter 3 output is above the low limit threshold
1: Comparator Filter 3 output is equal to or below the low level threshold, if enabled
High-level interrupt flag for Filter 3
0: Comparator Filter 3 output is below the high limit threshold
1: Comparator Filter 3 output is equal to or above the high level threshold, if enabled
Low-level interrupt flag for Filter 2
0: Comparator Filter 2 output is above the low limit threshold
1: Comparator Filter 2 output is equal to or below the low level threshold, if enabled
High-level interrupt flag for Filter 2
0: Comparator Filter 2 output is below the high limit threshold
1: Comparator Filter 2 output is equal to or above the high level threshold, if enabled
Low-level interrupt flag for Filter 1
0: Comparator Filter 1 output is above the low limit threshold
1: Comparator Filter 1 output is equal to or below the low level threshold, if enabled
High-level interrupt flag for Filter 1
0: Comparator Filter 1 output is below the high limit threshold
1: Comparator Filter 1 output is equal to or above the high level threshold, if enabled
Control Parameter Register (addresses 0x01, 0x07, 0x0D and 0x13)
The Control Parameter Registers control several parameters for the data acquisition process. The Control
Parameter Register functions include the Manchester decoder calibration status, clock pin direction control,
delta-sigma modulator mode select, sample-and-hold select and time measure mode. Table 14 describes the
Control Parameter Register.
Table 14. Control Parameter Register
Bit 15
MS10
Bit 14
MS9
Bit 13
MS8
Bit 12
MS7
Bit 11
MS6
Bit 10
MS5
Bit 9
MS4
Bit 8
MS3
Bit 7
MS2
Bit 6
MS1
Bit 5
MS0
Bit 4
CD
Bit 3
SHS
Bit 2
TM
Bit 1 Bit 0
MOD1 MOD0
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
R
R
R
R
R
R
R
R
R
R
R
RW
RW
RW
RW
RW
BIT POSITION
15–5
4
3
2
1–0
BIT
MS10–MS0
CD
SHS
TM
MOD1–MOD0
DESCRIPTION
Manchester status
Input clock direction.
0: Pin CLKx is an input
1: Pin CLKx is an output. The outgoing clock comes from the modulator clock divider.
Sample-and-hold select.
0: Signal SH1 is chosen as sample-and-hold signal
1: Signal SH2 is chosen as sample-and-hold signal
Time measure mode.
0: The time is measured from the last filter update to the last rising edge of the selected
sample-and-hold signal
1: The time is measured between two rising edges of the selected sample-and-hold signal
Delta-Sigma Modulator mode.
00: The clock speed is equal to the data rate from the modulator
01: The clock rate is half of the data rate from the modulator
10: The data from the modulator is Manchester decoded
11: The clock rate is twice the data rate of the modulator
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