AMC1210 Datasheet, PDF (29/47 Pages) Burr-Brown (TI) – Quad Digital Filter for 2nd-Order Delta-Sigma Modulator

AMC1210
www.ti.com
SBAS372A – APRIL 2006 – REVISED OCTOBER 2006
Sinc Filter Parameter Register (addresses 0x02, 0x08, 0x0E,and 0x14)
The Sinc Filter Parameter Register includes the oversampling ratio (OSR), filter enable, structure and signal
mode control bits. Table 15 shows the Sinc Filter Parameter Register.
Bit 15
–
Bit 14
–
Bit 13
–
Bit 12
–
Table 15. Sinc Filter Parameter Register
Bit 11
SST1
Bit 10
SST0
Bit 9
AE
Bit 8
FEN
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SOSR7 SOSR6 SOSR5 SOSR4 SOSR3 SOSR2 SOSR1 SOSR0
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
R
R
R
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
BIT POSITION
15–12
11–10
9
8
7–0
BIT
–
SST1–SST0
AE
FEN
SOSR7–SOSR0
DESCRIPTION
Unused. Always read '0'.
Sinc filter structure.
00: Sinc filter runs with a sincfast structure
01: Sinc filter runs with a Sinc¹ structure
10: Sinc filter runs with a Sinc² structure
11: Sinc filter runs with a Sinc³ structure
Acknowledge enable.
0: The acknowledge flag is disabled for the particular filter
1: The acknowledge flag is enabled for the particular filter
Filter enable.
0: The filter is disabled and no data is produced
1: The filter is enabled and data are produced in the sinc filter and/or integrator
Oversampling ratio. The actual rate is SOSR + 1.
These bits set the oversampling ratio of the filter.
0xFF represents an oversampling ratio of 256.
Integrator Parameter Register (addresses 0x03, 0x09, 0x0F and 0x15)
The Integrator Parameter Register controls the integrator functionality. It specifies the integrator oversampling
ratio, mode select, shift control, integrator and demodulation enable and data representation control bits.
Table 16 shows the Integrator Parameter Register.
Bit 15
SH4
Bit 14
SH3
Bit 13
SH2
Bit 12
SH1
Table 16. Integrator Parameter Register
Bit 11
SH0
Bit 10
DR
Bit 9
DEN
Bit 8
IEN
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IMOD IOSR6 IOSR5 IOSR4 IOSR3 IOSR2 IOSR1 IOSR0
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
BIT POSITION
15–11
10
9
8
7
6–0
BIT
SH4–SH0
DR
DEN
IEN
IMOD
IOSR6–IOSR0
DESCRIPTION
Shift control.
These bits indicate by how many bits the 16-bit window is shifted up when 16-bit data
representation is chosen.
Data representation.
0: The data is stored in 16-bit two's complement
1: The data is stored in 32-bit two's complement
Demodulation enable.
0: The demodulation for resolver applications is disabled
1: The demodulation for resolver applications is enabled
Integrator enable.
0: The data from the sinc filter output is stored in the register map
1: The data from the integrator is stored in the register map
Integrator mode.
0: The oversampling mode updates the data output of the integrator
1: The selected sample-and-hold signal updates the data output of the integrator
Oversampling ratio. The actual rate is IOSR + 1.
These bits set the oversampling ratio of the integrator.
0x03 represents an oversampling ratio of 4.
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