AMC1210 Datasheet, PDF (8/47 Pages) Burr-Brown (TI) – Quad Digital Filter for 2nd-Order Delta-Sigma Modulator

AMC1210
SBAS372A – APRIL 2006 – REVISED OCTOBER 2006
PARALLEL MODE 1
www.ti.com
TIMING CHARACTERISTICS⁽¹⁾
Over recommended operating free-air temperature range at –40°C to +125°C, DVDD = +5V, BVDD = +2.7V, unless otherwise noted.
PARAMETER ⁽²⁾
t_w1
CS low width
t_w2
CS high width
t_d1
Delay time from CS low to WR low
t_d2
Delay time from WR high to CS high
t_w3
WR low width
t_w4
WR high width
t_su1
Setup time from ALE high to WR low
t_h1
Hold time from WR high to ALE low
t_su2
Setup time from address valid to WR high
t_h2
Hold time from WR high to address invalid
t_d3
Delay time from CS low to RD low
t_d4
Delay time from RD high to CS high
t_w5
RD low width
t_w6
RD high width
t_d5
Delay time from RD low to data valid
t_d6
Delay time from RD high to databus in tristate
t_d7
Delay time from WR high to RD low
MIN
MAX
UNIT
40
ns
5
ns
3
ns
5
ns
10
ns
10
ns
0
ns
2
ns
6
ns
5
ns
0
ns
6
ns
30
ns
13
ns
30
ns
0
10
ns
10
ns
(1) All input signals are specified with t_R = t_F = 5ns (10% to 90% of BVDD) and timed from a voltage level of (V_IL + V_IH)/2.
(2) t_w2 is obsolete if CS stays low between the WR and RD pulses.
Parallel mode 1, write access
CS
t_w1
t_w2
t_d1
t_d2
WR
RD
t_su1
t_h1
ALE
AD(7:0)
ADDR
t_su2
t_h2
MSB
Internal address
ADDR
Parallel mode 1, read access
t_w3
t_w4
LSB
MSB
ADDR+1
CS
WR
RD
ALE
AD(7:0)
Internal address
t_d7
t_d4
t_d3
t_w6
t_w5
ADDR
ADDR
MSB
t_d5
t_d6
LSB
MSB
ADDR+1
Figure 4. Parallel Mode 1 Timing
8
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