AMC1210 Datasheet, PDF (32/47 Pages) Burr-Brown (TI) – Quad Digital Filter for 2nd-Order Delta-Sigma Modulator

AMC1210
SBAS372A – APRIL 2006 – REVISED OCTOBER 2006
www.ti.com
Control Register (address 0x19)
The Control Register controls the signal pattern generator and the interrupt and acknowledge pin behavior. It
specifies the interrupt and acknowledge pin polarities, the master interrupt enable and the signal pattern
generator length. Table 20 shows the Control Register.
Table 20. Control Register
Bit 15
AP
Bit 14
IP
Bit 13
MIE
Bit 12
–
Bit 11
–
Bit 10
–
Bit 9
PC9
Bit 8
PC8
Bit 7
PC7
Bit 6
PC6
Bit 5
PC5
Bit 4
PC4
Bit 3
PC3
Bit 2
PC2
Bit 1
PC1
Bit 0
PC0
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
RW
RW
RW
R
R
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
BIT POSITION
15
14
13
12–10
9–0
BIT
AP
IP
MIE
–
PC9–PC0
DESCRIPTION
Acknowledge polarity for pin ACK.
0: New data is signaled with a '1' on the pin ACK
1: New data is signaled with a '0' on the pin ACK
Interrupt polarity for pin INT.
0: An interrupt is signaled with a positive transition on the pin INT
1: An interrupt is signaled with a negative transition on the pin INT
Master interrupt enable.
0: Interrupt pin and interrupt flags are blocked (interrupt pin INT always inactive).
1: Interrupt pin and interrupt flags are not blocked and can be set and reset (if individually
enabled).
Unused. Always read '0'.
Pattern count.
Defines the length of the shift register for the signal generator
Pattern Register (address 0x1A)
The shift register of the signal generator is written through the Pattern Register. Each time this register is written,
the shift register is shifted 16 bits upwards and the written data is stored in the 16 LSBs of the shift register. The
Pattern Register is a write-only register; a read always returns 0x0000. Table 21 describes the Pattern Register.
Table 21. Pattern Register
Bit 15
SP15
Bit 14
SP14
Bit 13
SP13
Bit 12
SP12
Bit 11
SP11
Bit 10
SP10
Bit 9
SP9
Bit 8
SP8
Bit 7
SP7
Bit 6
SP6
Bit 5
SP5
Bit 4
SP4
Bit 3
SP3
Bit 2
SP2
Bit 1
SP1
Bit 0
SP0
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
'0'
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
BIT POSITION
15–0
BIT
SP15–SP0
Shift register pattern.
DESCRIPTION
32
Submit Documentation Feedback