PALCE29M16H-25 Datasheet, PDF (9/22 Pages) Advanced Micro Devices – 24-Pin EE CMOS Programmable Array Logic

Power-Up Reset
All flip-flops power up to a logic LOW for predictable sys-
tem initialization. The outputs of the PALCE29M16 de-
pend on whether they are selected as registered or
combinatorial. If registered is selected, the output will be
LOW if programmed as active LOW and HIGH if pro-
grammed as active HIGH. If combinatorial is selected,
the output will be a function of the logic.
Preload
To simplify testing, the PALCE29M16 is designed with
preload circuitry that provides an easy method for test-
ing logical functionality. Both product-term-controlled
and supervoltage-enabled preload modes are avail-
able. The TTL-level preload product term can be useful
during debugging, where supervoltages may not be
available.
Preload allows any arbitrary state value to be loaded
into the registers/latches of the device. A typical func-
tional-test sequence would be to verify all possible state
transitions for the device being tested. This requires the
ability to set the state registers into an arbitrary “present
state” value and to set the device’s inputs into an arbi-
trary “present input” value. Once this is done, the state
machine is clocked into a new state, or “next state,”
which can be checked to validate the transition from the
“present state.” In this way any transition can be
checked.
Since preload can provide the capability to go directly to
any desired arbitrary state, test sequences may be
greatly shortened. Also, all possible states can be
tested, thus greatly reducing test time and development
costs and guaranteeing proper in-system operation.
Observability
The output register/latch observability product term,
when asserted, suppresses the combinatorial output
data from appearing on the I/O pin and allows the obser-
vation of the contents of the register/latch on the output
AMD
pin for each of the logic macrocells. This unique feature
allows for easy debugging and tracing of the buried state
machines. In addition, a capability of supervoltage ob-
servability is also provided.
Security Cell
A security cell is provided on each device to prevent un-
authorized copying of the user’s proprietary logic de-
sign. Once programmed, the security cell disables the
programming, verification, preload, and the obser-
vability modes. The only way to erase the protection cell
is by erasing the entire array and architecture cells, in
which case no proprietary design can be copied. (This
cell should be programmed only after the rest of the de-
vice has been completely programmed and verified.)
Programming and Erasing
The PALCE29M16 can be programmed on standard
logic programmers. It may also be erased to reset a pre-
viously configured device back to its virgin state. Era-
sure is automatically performed by the programming
hardware. No special erasure operation is required.
Quality and Testability
The PALCE29M16 offers a very high level of built-in
quality. The erasability of the device provides a direct
means of verifying performance of all the AC and DC pa-
rameters. In addition, this verifies complete progr-
ammability and functionality of the device to yield the
highest programming yield and post-programming func-
tional yield in the industry.
Technology
The high-speed PALCE29M16 is fabricated with AMD’s
advanced electrically-erasable (EE) CMOS process.
The array connections are formed with proven EE cells.
Inputs and outputs are designed to be compatible with
TTL devices. This technology provides strong input-
clamp diodes, output slew-rate control, and a grounded
substrate for clean switching.
PALCE29M16H-25
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