PALCE29M16H-25 Datasheet, PDF (6/22 Pages) Advanced Micro Devices – 24-Pin EE CMOS Programmable Array Logic

AMD
Table 1a. PALCE29M16 I/O Logic Macrocell Architecture Selections
S3
I/O Cell
1
Output Cell
0
Input Cell
S2
Storage Element
1
Register
0
Latch
S1
Output Type
1
Combinatorial
0
Register/Latch
S0
Output Polarity
1
Active LOW
0
Active HIGH
S8
Feedback*
1
Register/Latch
0
I/O
*Applies to macrocells with single feedback only.
Table 1b. PALCE29M16 I/O Logic Macrocell Clock Polarity and Output Enable Selections
S4 S5 Clock Edge/Latch Enable Level
1
1 CLK/LE pin positive-going edge, active-LOW LE
1
0 CLK/LE pin negative-going edge, active-HIGH LE
0
1 I/CLK/LE pin positive-going edge, active-LOW LE
0
0 I/CLK/LE pin negative-going edge, active-HIGH LE
S6 S7 Output Buffer Control
1
1 Pin-Controlled Three-State Enable
1
0 XOR PT-Controlled Three-State Enable
0
1 Permanently Enabled (Output only)
0
0 Permanently Disabled (Input only)
Notes:
1 = Erased State (charged or disconnected).
0 = Programmed State (discharged or connected).
*Active-LOW LE means that data is stored when the LE pin is HIGH, and the latch is transparent when the LE pin is LOW.
Active-HIGH LE means the opposite.
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PALCE29M16H-25