PALCE29M16H-25 Datasheet, PDF (15/22 Pages) Advanced Micro Devices – 24-Pin EE CMOS Programmable Array Logic

SWITCHING CHARACTERISTICS
Latched Operation
Parameter
Symbol Parameter Description
Combinatorial Output
tPD
Input or I/O Pin to Combinatorial Output
tPTD
Input or I/O Pin to Output via One Transparent Latch
Output Latch
tSOL
Input or I/O Pin to Output Latch Setup
tGOL
Latch Enable to Output Through Transparent Output Latch
tHOL
Data Hold Time for Output Latch
tSTL
Input or I/O Pin to Output Latch Setup via Transparent Input Latch
Input Latch
tSIL
I/O Pin to Input Latch Setup
tGIL
Latch Feedback, Latch Enable Transparent Mode to Combinatorial Output
tHIL
Data Hold Time for Input Latch
Latch Enable
tGIS
Latch Feedback to Output Register/Latch Setup
tGWH
Pin Enable Width HIGH
tGWL
Pin Enable Width LOW
AMD
Min Max Unit
25
ns
28
ns
15
ns
15
ns
0
ns
18
ns
2
ns
28
ns
6
ns
20
ns
8
ns
8
ns
LE
AND-OR
tGIS
Array _tGIS
tSTL
Input
tSIL
Latch
tPTD
Output
tGOL
Latch
tPTD
I/O
I/O
I/O
I/O
tSOL
tGIL
tPTD
tPTD
tPD
tPD
08740G-25
Input/Output Latch Specs
PALCE29M16H-25 (Com’l)
2-341