PALCE29M16H-25 Datasheet, PDF (21/22 Pages) Advanced Micro Devices – 24-Pin EE CMOS Programmable Array Logic

POWER-UP RESET
The registered devices in the AMD PAL Family have
been designed with the capability to reset during system
power-up. Following power-up, all registers will be reset
to LOW. The output state will depend on the polarity of
the output buffer. This feature provides extra flexibility to
the designer and is especially valuable in simplifying
state machine initialization. A timing diagram and
parameter table are shown below. Due to the
Parameter
Symbol
tPR
tS
tW
tR
Parameter Description
Power-Up Reset Time
Input or Feedback Setup Time
Clock Width
VCC Rise Time
AMD
asynchronous operation of the power-up reset, and the
wide range of ways VCC can rise to its steady state, two
conditions are required to ensure a valid power-up re-
set. These conditions are:
The VCC rise must be monotonic.
Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and
feedback setup times are met.
Min
Max
Unit
10
µs
See Switching Characteristics
500
µs
Power
Registered
Active LOW
Output
Clock
4V
tR
tPR
tS
tW
Power-Up Reset Waveform
VCC
08740G-38
PALCE29M16H-25
2-347