PALCE29M16H-25 Datasheet, PDF (17/22 Pages) Advanced Micro Devices – 24-Pin EE CMOS Programmable Array Logic

SWITCHING CHARACTERISTICS
Reset/Preset, Enable
Parameter
Symbol Parameter Description
Combinatorial Output
tAPO
Input or I/O Pin to Output Register/Latch Reset/Preset
tAW
Asynchronous Reset/Preset Pulse Width
tARO
Asynchronous Reset/Preset to Output Register/Latch Recovery
tARI
Asynchronous Reset/Preset to Input Register/Latch Recovery
Output Enable Operation
tPZX
I/OE Pin to Output Enable
tPXZ
I/OE Pin to Output Disable (Note 1)
tEA
Input or I/O to Output Enable via PT
tER
Input or I/O to Output Disable via PT (Note 1)
Note:
1. Output disable times do not include test load RC time constants.
AMD
Min Max Unit
30
ns
15
ns
15
ns
12
ns
20
ns
20
ns
25
ns
25
ns
SWITCHING WAVEFORMS
.
Combinatorial
Asynchronous
Reset/Preset
Registered/Latched
Output
t _AW
t _APO
VT
t _ARO
Clock
VT
VT
Output Register/Latch Reset/Preset
08740G-31
Combinatorial
Asynchronous
Reset/Preset
Clock
Pin 11
VT
t _PXZ
Combinatorial/
Registered/
Latched Output
V _OH – 0.5 V
VOL + 0.5 V
t _PZX
VT
08740G-32
Pin 11 to Output Disable/Enable
t _AW
VT
t _ARI
VT
Input Register/Latch Reset/Preset
08740G-33
Combinatorial
Input
VT
t _ER
Combinatorial/
Registered/Latched
Output
VOH _{- 0.5 V}
VOL + 0.5 V
t _EA
VT
Input to Output Disable/Enable
08740G-34
PALCE29M16H-25 (Com’l)
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