PALCE29M16H-25 Datasheet, PDF (7/22 Pages) Advanced Micro Devices – 24-Pin EE CMOS Programmable Array Logic

AMD
SOME POSSIBLE CONFIGURATIONS OF THE INPUT/OUTPUT LOGIC MACROCELL
(For other useful configurations, please refer to the macrocell diagrams in Figure 2. All macrocell architecture cells are
independently programmable).
DQ
Q
S0 = 0
S1 = 0
S3 = 1
S2 = 1
08740G-6
Output Registered/Active Low
DQ
Q
S0 = 1
S1 = 1
S3 = 1
08740G-7
Output Combinatorial/Active Low
DQ
Q
S0 = 0
S1 = 0
S3 = 1
S2 = 1
DQ
Q
S0 = 0
S1 = 1
S3 = 1
08740G-8
Output Registered/Active High
08740G-9
Output Combinatorial/Active High
Figure 3a. Dual Feedback Macrocells
DQ
Q
S0 = 1
S1 = 0
S3 = 1
S8 = 0
S2 = 1
08740G-10
Output Registered/Active Low,
I/O Feedback
S0 = 1
S1 = 1
S3 = 1
S8 = 0
08740G-11
Output Combinatorial/Active Low,
I/O Feedback
DQ
LE Q
S0 = 0
S1 = 0
S3 = 1
S8 = 0
S2 = 0
08740G-12
S0 = 0
S1 = 1
S3 = 1
S8 = 0
08740G-13
Output Latched/Active High,
I/O Feedback
Output Combinatorial/Active High,
I/O Feedback
Figure 3b. Single Feedback Macrocells
PALCE29M16H-25
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