AM188ES-40KCW Datasheet, PDF (68/102 Pages) Advanced Micro Devices – High Performance, 80C186-/80C188-Compatible and 80L186-/80L188-Compatible, 16-Bit Embedded Microcontrollers

PRELIMINARY
SWITCHING CHARACTERISTICS over Commercial operating ranges
Read Cycle (20 MHz and 25 MHz)
Parameter
No. Symbol
Description
General Timing Requirements
1
t_DVCL Data in Setup
2
t_CLDX Data in Hold^(c)
General Timing Responses
3
t_CHSV Status Active Delay
4
t_CLSH Status Inactive Delay
5
t_CLAV AD Address Valid Delay and BHE
6
t_CLAX Address Hold
8
t_CHDX Status Hold Time
9
t_CHLH ALE Active Delay
10
t_LHLL ALE Width
11 t_CHLL ALE Inactive Delay
12
t_AVLL AD Address Valid to ALE Low^(a)
13 t_LLAX AD Address Hold from ALE
Inactive^(a)
14 t_AVCH AD Address Valid to Clock High
15 t_CLAZ AD Address Float Delay
16 t_CLCSV MCS/PCS Active Delay
17 t_CXCSX MCS/PCS Hold from Command
Inactive^(a)
18 t_CHCSX MCS/PCS Inactive Delay
19
t_DXDL DEN Inactive to DT/R Low^(a)
20 t_CVCTV Control Active Delay 1^(b)
21 t_CVDEX DEN Inactive Delay
22 t_CHCTV Control Active Delay 2^(b)
23 t_LHAV ALE High to Address Valid
99
t_PLAL PCS Low to ALE Low
Read Cycle Timing Responses
24 t_AZRL AD Address Float to RD Active
25 t_CLRL RD Active Delay
26
t_RLRH
RD Pulse Width
27 t_CLRH RD Inactive Delay
28
t_RHLH RD Inactive to ALE High^(a)
29 t_RHAV RD Inactive to AD Address
Active^(a)
41 t_DSHLH DS Inactive to ALE High
59 t_RHDX RD High to Data Hold on AD Bus^(c)
66
t_AVRL A Address Valid to RD Low^(a)
67 t_CHCSV CLKOUTA High to LCS/UCS Valid
68 t_CHAV CLKOUTA High to A Address
Valid
Preliminary
20 MHz
25 MHz
Min
Max
Min
Max
10
10
3
3
0
25
0
20
0
25
0
20
0
25
0
20
0
25
0
20
0
0
25
20
t_CLCL – 10 =
40
t_CLCL – 10 =
30
25
20
t_{CLCH L} – 2
t_CHCL –2
t_CLCH – 2
t_CHCL – 2
0
0
t_CLAX = 0
25
t_CLAX = 0
20
0
25
0
20
t_CLCH – 2
t_CLCH – 2
0
25
0
20
0
0
0
25
0
20
0
12
0
12
0
25
0
20
20
15
15
28
15
24
0
0
0
25
0
20
2t_CLCL – 15 =
85
2t_CLCL – 15 =
65
0
25
0
20
t_CLCH – 3
t_CLCL – 10 =
40
t_CLCH – 3
t_CLCL – 10 =
30
t_CLCH – 2=
21
t_CLCH – 2=
16
0
0
t_CLCL +
t_CLCL +
t_CHCL–3
t_CHCL–3
0
25
0
20
0
25
0
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions
are with C_L =50 pF. For switching tests, V_IL=0.45 V and V_IH =2.4 V, except at X1 where V_IH =V_CC – 0.5 V.
a Equal loading on referenced pins.
b This parameter applies to the DEN, DS, INTA1–INTA0, WR, WHB, and WLB signals.
c If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.
68
Am186/188ES and Am186/188ESLV Microcontrollers