AM188ES-40KCW Datasheet, PDF (47/102 Pages) Advanced Micro Devices – High Performance, 80C186-/80C188-Compatible and 80L186-/80L188-Compatible, 16-Bit Embedded Microcontrollers

PRELIMINARY
for a ready signal. This behavior may occur even in a
system in which ready is always asserted (ARDY or
SRDY tied High).
Configuring PCS in I/O space with LCS or any other
chip select configured for memory address 0 is not con-
sidered overlapping of the chip selects. Overlapping
chip selects refers to configurations where more than
one chip select asserts for the same physical address.
Upper Memory Chip Select
The Am186ES and Am188ES microcontrollers provide
a UCS chip select for the top of memory. On reset the
Am186ES and Am188ES microcontrollers begin fetch-
ing and executing instructions at memory location
FFFF0h. Therefore, upper memory is usually used as
instruction memory. To facilitate this usage, UCS de-
faults to active on reset, with a default memory range of
64 Kbytes from F0000h to FFFFFh, with external ready
required and three wait states automatically inserted.
The UCS memory range always ends at FFFFFh. The
UCS lower boundary is programmable.
Low Memory Chip Select
The Am186ES and Am188ES microcontrollers provide
an LCS chip select for lower memory. The AUXCON
register can be used to configure LCS for 8-bit or 16-bit
accesses. Since the interrupt vector table is located at
the bottom of memory starting at 00000h, the LCS pin
is usually used to control data memory. The LCS pin is
not active on reset.
Midrange Memory Chip Selects
The Am186ES and Am188ES microcontrollers provide
four chip selects, MCS3–MCS0, for use in a user-locat-
able memory block. With some exceptions, the base
address of the memory block can be located anywhere
within the 1-Mbyte memory address space of the
Am186ES and Am188ES microcontrollers. The areas
associated with the UCS and LCS chip selects are ex-
cluded. If they are mapped to memory, the address
range of the peripheral chip selects, PCS6, PCS5, and
PCS3–PCS0, are also excluded. The MCS address
range can overlap the PCS address range if the PCS
chip selects are mapped to I/O space.
MCS0 can be configured to be asserted for the entire
MCS range. When configured in this mode, the MCS3–
MCS1 pins can be used as PIOs.
The AUXCON register can be used to configure MCS
for 8-bit or 16-bit accesses. The bus width of the MCS
range is determined by the width of the non-UCS/non-
LCS memory range.
Unlike the UCS and LCS chip selects, the MCS outputs
assert with the same timing as the multiplexed AD ad-
dress bus.
Peripheral Chip Selects
The Am186ES and Am188ES microcontrollers provide
six chip selects, PCS6–PCS5 and PCS3–PCS0, for
use within a user-configured memory or I/O block.
PCS4 is not available on the Am186ES and Am188ES
microcontrollers. The base address of the memory
block can be located anywhere within the 1-Mbyte
memory address space, exclusive of the areas associ-
ated with the UCS, LCS, and MCS chip selects, or they
can be configured to access the 64-Kbyte I/O space.
The PCS pins are not active on reset. PCS6–PCS5 can
be programmed for zero to three wait states. PCS3–
PCS0 can be programmed for four additional wait-state
values: 5, 7, 9, and 15.
The AUXCON register can be used to configure PCS
for 8-bit or 16-bit accesses. The bus width of the PCS
range is determined by the width of the non-UCS/non-
LCS memory range or by the width of the I/O area.
Unlike the UCS and LCS chip selects, the PCS outputs
assert with the multiplexed AD address bus. Each
peripheral chip select asserts over a 256-byte address
range, which is twice the address range covered by
peripheral chip selects in the 80C186/188 microcon-
trollers.
REFRESH CONTROL UNIT
The Refresh Control Unit (RCU) automatically gener-
ates refresh bus cycles. After a programmable period
of time, the RCU generates a memory read request to
the bus interface unit. The RCU is fixed to three wait
states for the PSRAM auto refresh mode.
In the Am186ES and Am188ES microcontrollers, re-
fresh is enabled when the ENA bit is set in the enable
RCU register, offset E4h. This is different from the
Am186EM and Am188EM microcontrollers where the
PSRAM enable bit in the low memory chip-select reg-
ister, offset A2h, enables refresh. The refresh function
is the same as on the Am186EM and Am188EM micro-
controllers, except that the DRAM address is not driven
on DRAM refreshes.
If the HLDA pin is active when a refresh request is gen-
erated (indicating a bus hold condition), the Am186ES
and Am188ES microcontrollers deactivate the HLDA
pin in order to perform a refresh cycle. The external bus
master must remove the HOLD signal for at least one
clock in order to allow the refresh cycle to execute.
Am186/188ES and Am186/188ESLV Microcontrollers
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