AM188ES-40KCW Datasheet, PDF (35/102 Pages) Advanced Micro Devices – High Performance, 80C186-/80C188-Compatible and 80L186-/80L188-Compatible, 16-Bit Embedded Microcontrollers

PRELIMINARY
RD
Read Strobe (output, synchronous, three-state)
RD—This pin indicates to the system that the
microcontroller is performing a memory or I/O read
cycle. RD is guaranteed to not be asserted before the
address and data bus is floated during the address-to-
data transition. RD floats during a bus hold condition.
RES
Reset (input, asynchronous, level-sensitive)
This pin requires the microcontroller to perform a reset.
When RES is asserted, the microcontroller
immediately terminates its present activity, clears its
internal logic, and transfers CPU control to the reset
address, FFFF0h.
RES must be held Low for at least 1 ms.
RES can be asserted asynchronously to CLKOUTA
because RES is synchronized internally. For proper
initialization, V_CC must be within specifications, and
CLKOUTA must be stable for more than four
CLKOUTA periods during which RES is asserted.
The microcontroller begins fetching instructions
approximately 6.5 CLKOUTA periods after RES is
deasserted. This input is provided with a Schmitt
trigger to facilitate power-on RES generation via an RC
network.
RFSH2/ADEN
(Am188ES Microcontroller Only)
Refresh 2 (three-state, output, synchronous)
Address Enable (input, internal pullup)
RFSH2—Asserted Low to signify a DRAM refresh bus
cycle. The use of RFSH2/ADEN to signal a refresh is
not valid when PSRAM mode is selected. Instead, the
MCS3/RFSH signal is provided to the PSRAM.
ADEN—If RFSH2/ADEN is held High or left floating on
power-on reset, the AD bus (AO15–AO8 and AD7–
AD0) is enabled or disabled during the address portion
of LCS and UCS bus cycles based on the DA bit in the
LMCS and UMCS registers. If the DA bit is set, the
memory address is accessed on the A19–A0 pins. This
mode of operation reduces power consumption. For
more information, see the “Bus Operation” section on
page 39. There is a weak internal pullup resistor on
RFSH2/ADEN so no external pullup is required.
If RFSH2/ADEN is held Low on power-on reset, the AD
bus drives both addresses and data, regardless of the
DA bit setting. The pin is sampled one crystal clock
cycle after the rising edge of RES. RFSH2/ADEN is
three-stated during bus holds and ONCE mode.
RTS0/RTR0/PIO20
Ready-to-Send 0 (output, asynchronous)
Ready-to-Receive 0 (output, asynchronous)
RTS0—This pin provides the Ready to Send signal for
asynchronous serial port 0 when the RTS0 bit in the
AUXCON register is 1 and hardware flow control is
enabled for the port (FC bit in the serial port 0 control
register is set). The RTS0 signal is asserted when the
associated serial port transmit register contains data
that has not been transmitted.
RTR0—This pin provides the Ready to Receive signal
for asynchronous serial port 0 when the RTS0 bit in the
AUXCON register is 0 and hardware flow control is
enabled for the port (FC bit in the serial port 0 control
register is set). The RTR0 signal is asserted when the
associated serial port receive register does not contain
valid, unread data.
RXD0/PIO23
Receive Data 0 (input, asynchronous)
This pin supplies asynchronous serial receive data
from the system to asynchronous serial port 0.
RXD1/PIO28
Receive Data 1 (input, asynchronous)
This pin supplies asynchronous serial receive data
from the system to asynchronous serial port 1.
S2–S0
Bus Cycle Status (output, three-state,
synchronous)
These pins indicate to the system the type of bus cycle
in progress. S2 can be used as a logical memory or I/
O indicator, and S1 can be used as a data transmit or
receive indicator. S2–S0 float during bus hold and hold
acknowledge conditions. The S2–S0 pins are encoded
as shown in Table 4.
Table 4. Bus Cycle Encoding
S2
S1
S0
Bus Cycle
0
0
0 Interrupt acknowledge
0
0
1 Read data from I/O
0
1
0 Write data to I/O
0
1
1 Halt
1
0
0 Instruction fetch
1
0
1 Read data from memory
1
1
0 Write data to memory
1
1
1 None (passive)
Am186/188ES and Am186/188ESLV Microcontrollers
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