AM188ES-40KCW Datasheet, PDF (29/102 Pages) Advanced Micro Devices – High Performance, 80C186-/80C188-Compatible and 80L186-/80L188-Compatible, 16-Bit Embedded Microcontrollers

PRELIMINARY
DEN/DS/PIO5
Data Enable (output, three-state, synchronous)
Data Strobe (output, three-state, synchronous)
DEN—This pin supplies an output enable to an
external data-bus transceiver. DEN is asserted during
memory, I/O, and interrupt acknowledge cycles. DEN
is deasserted when DT/R changes state. DEN floats
during a bus hold or reset condition.
DS—The data strobe provides a signal where the write
cycle timing is identical to the read cycle timing. When
used with other control signals, DS provides an
interface for 68K-type peripherals without the need for
additional system interface logic.
When DS is asserted, addresses are valid. When DS is
asserted on writes, data is valid. When DS is asserted
on reads, data can be asserted on the AD bus.
Note: This pin resets to DEN.
DRQ0/INT5/PIO12
DMA Request 0 (input, synchronous,
level-sensitive)
Maskable Interrupt Request 5 (input,
asynchronous, edge-triggered)
DRQ0—This pin indicates to the microcontroller that an
external device is ready for DMA channel 0 to perform a
transfer. DRQ0 is level-triggered and internally synchronized.
DRQ0 is not latched and must remain active until
serviced.
INT5—If DMA 0 is not enabled or DMA 0 is not being
used with external synchronization, INT5 can be used
as an additional external interrupt request. INT5 shares
the DMA 0 interrupt type (0Ah) and register control bits.
INT5 is edge-triggered only and must be held until the
interrupt is acknowledged.
DRQ1/INT6/PIO13
DMA Request 1 (input, synchronous,
level-sensitive)
Maskable Interrupt Request 6 (input,
asynchronous, edge-triggered)
DRQ1—This pin indicates to the microcontroller that an
external device is ready for DMA channel 1 to perform
a transfer. DRQ1 is level-triggered and internally
synchronized.
DRQ1 is not latched and must remain active until
serviced.
INT6—If DMA 1 is not enabled or DMA 1 is not being
used with external synchronization, INT6 can be used
as an additional external interrupt request. INT6 shares
the DMA 1 interrupt type (0Bh) and register control bits.
INT6 is edge-triggered only and must be held until the
interrupt is acknowledged.
DT/R/PIO4
Data Transmit or Receive (output, three-state,
synchronous)
This pin indicates in which direction data should flow
through an external data-bus transceiver. When DT/R
is asserted High, the microcontroller transmits data.
When this pin is deasserted Low, the microcontroller
receives data. DT/R floats during a bus hold or reset
condition.
GND
Ground
Ground pins connect the microcontroller to the system
ground.
HLDA
Bus Hold Acknowledge (output, synchronous)
This pin is asserted High to indicate to an external bus
master that the microcontroller has released control of
the local bus. When an external bus master requests
control of the local bus (by asserting HOLD), the
microcontroller completes the bus cycle in progress. It
then relinquishes control of the bus to the external bus
master by asserting HLDA and floating DEN, RD, WR,
S2–S0, AD15–AD0, S6, A19–A0, BHE, WHB, WLB,
and DT/R, and then driving the chip selects UCS, LCS,
MCS3–MCS0, PCS6–PCS5, and PCS3–PCS0 High.
When the external bus master has finished using the
local bus, it indicates this to the microcontroller by
deasserting HOLD. The microcontroller responds by
deasserting HLDA.
If the microcontroller requires access to the bus (for
example, to refresh), it will deassert HLDA before the
external bus master deasserts HOLD. The external bus
master must be able to deassert HOLD and allow the
microcontroller access to the bus. See the timing
diagrams for bus hold on page 97.
HOLD
Bus Hold Request (input, synchronous,
level-sensitive)
This pin indicates to the microcontroller that an external
bus master needs control of the local bus.
The Am186ES and Am188ES microcontrollers’ HOLD
latency time is a function of the activity occurring in the
processor when the HOLD request is received. A
DRAM request will delay a HOLD request when both
requests are made at the same time. In addition, if
locked transfers are performed, the HOLD latency time
is increased by the length of the locked transfer.
For more information, see the HLDA pin description on
page 29.
Am186/188ES and Am186/188ESLV Microcontrollers
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