AM188ES-40KCW Datasheet, PDF (39/102 Pages) Advanced Micro Devices – High Performance, 80C186-/80C188-Compatible and 80L186-/80L188-Compatible, 16-Bit Embedded Microcontrollers

PRELIMINARY
BUS OPERATION
The industry-standard 80C186 and 80C188 microcon-
trollers use a multiplexed address and data (AD) bus.
The address is present on the AD bus only during the
t1 clock phase. The Am186ES and Am188ES micro-
controllers continue to provide the multiplexed AD bus
and, in addition, provide a nonmultiplexed address (A)
bus. The A bus provides an address to the system for
the complete bus cycle (t1–t4).
For systems where power consumption is a concern, it
is possible to disable the address from being driven on
the AD bus on the Am186ES microcontroller and on the
AD and AO buses on the Am188ES microcontroller
during the normal address portion of the bus cycle for
accesses to UCS and/or LCS address spaces. In this
mode, the affected bus is placed in a high-impedance
state during the address portion of the bus cycle. This
feature is enabled through the DA bits in the UMCS and
LMCS registers. When address disable is in effect, the
number of signals that assert on the bus during all nor-
mal bus cycles to the associated address space is re-
duced, decreasing power consumption and reducing
processor switching noise. On the Am188ES micro-
controller, the address is driven on A015–A08 during
the data portion of the bus cycle regardless of the set-
ting of the DA bits.
If the ADEN pin is pulled Low during processor reset,
the value of the DA bits in the UMCS and LMCS regis-
ters is ignored and the address is driven on the AD bus
for all accesses, thus preserving the industry-standard
80C186 and 80C188 microcontrollers’ multiplexed ad-
dress bus and providing support for existing emulation
tools.
The following diagrams show the Am186ES and
AM188ES microcontroller bus cycles when the ad-
dress bus disable feature is in effect:
n Figure 4 shows the affected signals during a normal
read or write operation for an Am186ES microcon-
troller. The address and data are multiplexed onto
the AD bus.
n Figure 5 shows an Am186ES microcontroller bus
cycle when address bus disable is in effect. This re-
sults in the AD bus operating in a nonmultiplexed
address/data mode. The A bus has the address
during a read or write operation.
n Figure 6 shows the affected signals during a normal
read or write operation for an Am188ES microcon-
troller. The multiplexed address/data mode is com-
patible with the 80C186 and 80C188
microcontrollers and might be used to take advan-
tage of existing logic or peripherals.
n Figure 7 shows an Am188ES microcontroller bus
cycle when address bus disable is in effect. The ad-
dress and data is not multiplexed. The AD7–AD0
signals have only data on the bus, while the AO bus
has the address during a read or write operation.
CLKOUTA
A19–A0
AD15–AD0
(Read)
AD15–AD0
(Write)
LCS or UCS
MCSx, PCSx
t₁
t₂
t₃
t₄
Address
Data
Phase
Phase
Address
Address
Data
Address
Data
Figure 4. Am186ES Microcontroller Address Bus—Normal Read and Write Operation
Am186/188ES and Am186/188ESLV Microcontrollers
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