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EP3C55F780I7 Datasheet, PDF (91/274 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Cyclone III device family | |||
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Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
PLL Reconfiguration
5â31
Table 5â7. Loop Filter Control of High Frequency Capacitor
LFC[1]
0
0
1
LFC[0]
0
1
1
Setting (Decimal)
0
1
3
Bypassing PLL Counter
Bypassing a PLL counter results in a multiply (M counter) or a divide (N, C0 to C4
counters) factor of one.
Table 5â8 lists the settings for bypassing the counters in Cyclone III device family
PLLs.
Table 5â8. PLL Counter Settings
PLL Scan Chain Bits [0..8] Settings
LSB
XXXXXXXX
XXXXXXXX
Note to Table 5â8:
(1) Bypass bit.
Description
MSB
1 (1) PLL counter bypassed
0 (1) PLL counter not bypassed
To bypass any of the PLL counters, set the bypass bit to 1. The values on the other bits
are then ignored.
Dynamic Phase Shifting
The dynamic phase shifting feature allows the output phase of individual PLL
outputs to be dynamically adjusted relative to each other and the reference clock
without sending serial data through the scan chain of the corresponding PLL. This
feature simplifies the interface and allows you to quickly adjust tCO delays by
changing output clock phase shift in real time. This is achieved by incrementing or
decrementing the VCO phase-tap selection to a given C counter or to the M counter.
The phase is shifted by 1/8 the VCO frequency at a time. The output clocks are active
during this phase reconfiguration process.
Table 5â9 lists the control signals that are used for dynamic phase shifting.
Table 5â9. Dynamic Phase Shifting Control Signals (Part 1 of 2)
Signal Name
Description
Source
PHASECOUNTERSELECT[2:0]
PHASEUPDOWN
Counter Select. Three bits decoded to select
either the M or one of the C counters for
phase adjustment. One address map to select
all C counters. This signal is registered in the
PLL on the rising edge of SCANCLK.
Selects dynamic phase shift direction; 1= UP,
0 = DOWN. Signal is registered in the PLL on
the rising edge of SCANCLK.
Logic array or I/O
pins
Logic array or I/O
pins
Destination
PLL
reconfiguration
circuit
PLL
reconfiguration
circuit
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
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