EP3C55F780I7 Datasheet, PDF (145/274 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Cyclone III device family

Chapter 8: External Memory Interfaces in the Cyclone III Device Family
8–3
Cyclone III Device Family Memory Interfaces Pin Support
1 Cyclone III device family does not support differential strobe pins, which is an
optional feature in the DDR2 SDRAM device.
f When you use the Altera Memory Controller MegaCore^®, the PHY is instantiated for
you. For more information about the memory interface data path, refer to the External
Memory Interfaces page.
1 ALTMEMPHY is a self-calibrating megafunction, enhanced to simplify the
implementation of the read-data path in different memory interfaces. The
auto-calibration feature of ALTMEMPHY provides ease-of-use by optimizing clock
phases and frequencies across process, voltage, and temperature (PVT) variations.
You can save on the global clock resources in Cyclone III device family through the
ALTMEMPHY megafunction because you are not required to route the DQS signals on
the global clock buses (because DQS is ignored for read capture). Resynchronization
issues do not arise because no transfer occurs from the memory domain clock (DQS) to
the system domain for capturing data DQ.
All I/O banks in Cyclone III device family can support DQ and DQS signals with DQ-bus
modes of ×8, ×9, ×16, ×18, ×32, and ×36. DDR2 and DDR SDRAM interfaces use ×8
mode DQS group regardless of the interface width. For wider interface, you can use
multiple ×8 DQ groups to achieve the desired width requirement.
In the ×9, ×18, and ×36 modes, a pair of complementary DQS pins (CQ and CQ#)
drives up to 9, 18, or 36 DQ pins, respectively, in the group, to support one, two, or four
parity bits and the corresponding data bits. The ×9, ×18, and ×36 modes support the
QDR II memory interface. CQ# is the inverted read-clock signal which is connected to
the complementary data strobe (DQS or CQ#) pin. You can use any unused DQ pins as
regular user I/O pins if they are not used as memory interface signals.
Table 8–1 lists the number of DQS or DQ groups supported on each side of the
Cyclone III device only.
Table 8–1. Cyclone III Device DQS and DQ Bus Mode Support for Each Side of the Device (Part 1 of 4)
Device
Package
Number Number Number Number Number Number
Side
×8
×9
×16
×18
×32
×36
Groups Groups Groups Groups Groups Groups
EP3C5
Left
0
0
0
144-pin EQFP ⁽¹⁾
Right
Top ⁽²⁾
0
0
0
1
0
0
Bottom ^{(3), (4)}
1
0
0
Left
0
0
0
164-pin MBGA ⁽¹⁾
Right
Top ⁽²⁾
0
0
0
1
0
0
Bottom ^{(3), (4)}
1
0
0
256-pin FineLine Left ^{(4), (5)}
1
1
0
BGA/256-pin
Right ^{(4), (6)}
1
1
0
Ultra FineLine
BGA ⁽¹⁾
Top
Bottom
2
2
1
2
2
1
0
—
—
0
—
—
0
—
—
0
—
—
0
—
—
0
—
—
0
—
—
0
—
—
0
—
—
0
—
—
1
—
—
1
—
—
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1