EP3C55F780I7 Datasheet, PDF (268/274 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Cyclone III device family

12–4
Chapter 12: IEEE 1149.1 (JTAG) Boundary-Scan Testing for the Cyclone III Device Family
IEEE Std. 1149.1 BST Operation Control
Table 12–3. IEEE Std. 1149.1 (JTAG) Instructions Supported by Cyclone III Device Family (Part 2 of 2)
JTAG Instruction
FACTORY ⁽⁴⁾
KEY_PROG_VOL ⁽⁴⁾
KEY_CLR_VREG ⁽⁴⁾
Instruction Code
Description
10 1000 0001
Enables access to all other JTAG instructions (other than BYPASS,
SAMPLE/PRELOAD and EXTEST instructions, which are supported upon
power up). This instruction also clears the device configuration data
and advanced encryption standard (AES) volatile key.
01 1010 1101
00 0010 1001
Used to enter and store the security key into volatile registers. When
this instruction is executed, TDI is connected to a 512-bit volatile key
scan chain. TDO is not connected to the end of this scan chain.
Clears the volatile verify register which signifies the validity of the
volatile keys stored in the registers. You must clear the volatile verify
register by issuing this command whenever you attempt to program a
new volatile key. This instruction must be asserted for at least 10 TCK
cycles.
Notes to Table 12–3:
(1) Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST.
(2) For more information about how to use CONFIG_IO, EN_ACTIVE_CLK, DIS_ACTIVE_CLK, ACTIVE_DISENGAGE, ACTIVE_ENGAGE and
APFC_BOOT_ADDR instructions for Cyclone III device family, refer to the Configuration, Design Security, and Remote System Upgrades in
Cyclone III Devices chapter.
(3) APFC_BOOT_ADDR instruction is not supported in Cyclone III LS devices.
(4) For Cyclone III LS devices only. For more information about how to program the security key into the volatile registers, refer to the
Configuration, Design Security, and Remote System Upgrades in Cyclone III Devices chapter.
The IEEE Std. 1149.1 BST circuitry is enabled upon device power-up. You can perform
BST on Cyclone III device family before, after, and during configuration. Cyclone III
device family supports the BYPASS, IDCODE and SAMPLE instructions during
configuration without interrupting configuration. To send all other JTAG instructions,
interrupt the configuration using the CONFIG_IO instruction except for active
configuration schemes in which the ACTIVE_DISENGAGE instruction is used instead.
The CONFIG_IO instruction allows you to configure I/O buffers via the JTAG port, and
when issued, interrupts configuration. This instruction allows you to perform board-
level testing prior to configuring Cyclone III device family. Alternatively, you can wait
for the configuration device to complete configuration. After configuration is
interrupted and JTAG BST is complete, you must reconfigure the part via JTAG
(PULSE_NCONFIG instruction) or by pulsing nCONFIG low.
1 When you perform JTAG boundary-scan testing before configuration, the nCONFIG pin
must be held low.
f For more information about the following topics, refer to AN39: IEEE 1149.1 (JTAG)
Boundary-Scan Testing in Altera Devices:
■ TAP controller state-machine
■ Timing requirements for IEEE Std. 1149.1 signals
■ Instruction mode
■ Mandatory JTAG instructions (SAMPLE/PRELOAD, EXTEST and BYPASS)
■ Optional JTAG instructions (IDCODE, USERCODE, CLAMP and HIGHZ)
The following information is only applicable to Cyclone III LS devices:
Cyclone III Device Handbook
Volume 1
December 2011 Altera Corporation