EP3C55F780I7 Datasheet, PDF (207/274 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Cyclone III device family

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
9–49
f For more information about how to connect a JTAG chain with multiple voltages
across the devices in the chain, refer to the IEEE 1149.1 (JTAG) Boundary-Scan Testing
for Cyclone III Devices chapter.
Table 9–15. Dedicated JTAG Pins
Pin
Name
TDI
TDO
TMS
TCK
Pin Type
Test data input
Test data output
Test mode select
Test clock input
Description
Serial input pin for instructions as well as test and programming data. Data shifts in on the
rising edge of TCK. The TDI pin is powered by the V_CCIO supply. If the JTAG interface is not
required on the board, the JTAG circuitry is disabled by connecting this pin to V_CC.
Serial data output pin for instructions as well as test and programming data. Data shifts out on
the falling edge of TCK. The pin is tri-stated if data is not being shifted out of the device. The
TDO pin is powered by V_CCIO in I/O bank 1. If the JTAG interface is not required on the board, the
JTAG circuitry is disabled by leaving this pin unconnected.
Input pin that provides the control signal to determine the transitions of the TAP controller state
machine. Transitions in the state machine occur on the rising edge of TCK. Therefore, TMS must
be set up before the rising edge of TCK. TMS is evaluated on the rising edge of TCK. The TMS pin
is powered by the V_CCIO supply. If the JTAG interface is not required on the board, the JTAG
circuitry is disabled by connecting this pin to V_CC.
Clock input to the BST circuitry. Some operations occur at the rising edge while others occur at
the falling edge. The TCK pin is powered by the V_CCIO supply. If the JTAG interface is not
required on the board, the JTAG circuitry is disabled by connecting this pin to GND.
You can download data to the device on the PCB through the USB-Blaster,
MasterBlaster, ByteBlaster II, ByteBlasterMV download cable, and Ethernet-Blaster
communications cable during JTAG configuration. Configuring devices using a cable
is similar to programming devices in-system. Figure 9–24 and Figure 9–25 show the
JTAG configuration of a single Cyclone III device family.
For device V_CCIO of 2.5, 3.0, and 3.3 V, refer to Figure 9–24. All I/O inputs must
maintain a maximum AC voltage of 4.1 V. Because JTAG pins do not have the internal
PCI clamping diodes to prevent voltage overshoot when using V_CCIO of 2.5, 3.0, and
3.3 V, you must power up the V_CC of the download cable with a 2.5-V supply from
V_CCA, and you must pull TCK to ground.
August 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1