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EP3C55F780I7 Datasheet, PDF (107/274 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Cyclone III device family | |||
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Chapter 6: I/O Features in the Cyclone III Device Family
6â9
OCT Support
Figure 6â3 shows the top-level view of the OCT calibration blocks placement.
Figure 6â3. Cyclone III Device Family OCT Block Placement
I/O Bank 8
I/O Bank 7
Cyclone III Device Family
I/O Bank 3
I/O Bank 4
I/O bank with
calibration block
I/O bank without
calibration block
Calibration block
coverage
Each calibration block comes with a pair of RUP and RDN pins. When used for
calibration, the RUP pin is connected to VCCIO through an external 25-ï ±1% or
50-ï ±1% resistor for an on-chip series termination value of 25 ï or 50 ï ,
respectively. The RDN pin is connected to GND through an external 25-ï ±1% or 50-ï
±1% resistor for an on-chip series termination value of 25 ï or 50 ï , respectively. The
external resistors are compared with the internal resistance using comparators. The
resultant outputs of the comparators are used by the OCT calibration block to
dynamically adjust buffer impedance.
During calibration, the resistance of the RUP and RDN pins varies. For an estimate of the
maximum possible current through the external calibration resistors, assume a
minimum resistance of 0 ï on the RUP and RDN pins during calibration.
July 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
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