EP3C55F780I7 Datasheet, PDF (137/274 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Cyclone III device family

Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
True Output Buffer Feature
7–15
Figure 7–13 shows the differential HSTL Class II interface.
Figure 7–13. Differential HSTL Class II Interface
VTT
VTT
VTT
VTT
Output Buffer (1)
50 Ω
50 Ω
Z0 = 50 Ω
50 Ω
50 Ω
Receiver
Z0 = 50 Ω
Note to Figure 7–13:
(1) PLL output clock pins do not support differential HSTL Class II I/O standard.
True Output Buffer Feature
Cyclone III device family true differential transmitters offer programmable
pre-emphasis—you can choose to turn it on or off. The default setting is on.
Programmable Pre-Emphasis
The programmable pre-emphasis boosts the high frequencies of the output signal to
compensate the frequency-dependent attenuation of the transmission line to
maximize the data eye opening at the far-end receiver. Without pre-emphasis, the
output current is limited by the V_OD specification and the output impedance of the
transmitter. At high frequency, the slew rate may not be fast enough to reach full V_OD
before the next edge; this may lead to pattern dependent jitter. With pre-emphasis, the
output current is momentarily boosted during switching to increase the output slew
rate. The overshoot produced by this extra switching current is different from the
overshoot caused by signal reflection. This overshoot happens only during switching,
and does not produce ringing.
Figure 7–14 shows the differential output signal with pre-emphasis.
Figure 7–14. The Output Signal with Pre-Emphasis
Overshoot
Positive channel (p)
V_OD
Negative channel (n)
Undershoot
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1