EP3C55F780I7 Datasheet, PDF (135/274 Pages) Altera Corporation – This section provides a complete overview of all features relating to the Cyclone III device family

Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
High-Speed I/O Standards Support
7–13
Figure 7–9 shows the LVPECL DC-coupled termination.
Figure 7–9. LVPECL DC-Coupled Termination
LVPECL Transmitter
50 
50 
Cyclone III Device Family
LVPECL Receiver
100 
Differential SSTL I/O Standard Support in the Cyclone III Device Family
The differential SSTL I/O standard is a memory-bus standard used for applications
such as high-speed DDR SDRAM interfaces. The Cyclone III device family supports
differential SSTL-2 and SSTL-18 I/O standards. The differential SSTL output standard
is only supported at PLL#_CLKOUT pins using two single-ended SSTL output buffers
(PLL#_CLKOUTp and PLL#_CLKOUTn), with the second output programmed to have
opposite polarity. The differential SSTL input standard is supported on the GCLK
pins only, treating differential inputs as two single-ended SSTL and only decoding
one of them.
The differential SSTL I/O standard requires two differential inputs with an external
reference voltage (VREF) as well as an external termination voltage (VTT) of 0.5 × V_CCIO
to which termination resistors are connected.
f For more information about the differential SSTL electrical specifications, refer to the
I/O Features in the Cyclone III Device Family chapter and the Cyclone III Device Data Sheet
and Cyclone III LS Device Data Sheet chapters.
Figure 7–10 shows the differential SSTL Class I interface.
Figure 7–10. Differential SSTL Class I Interface
V_TT
V_TT
Output Buffer
Receiver
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1