EP2C8Q208C6 Datasheet, PDF (76/168 Pages) Altera Corporation – Section I. Cyclone II Device Family Data Sheet

IEEE Std. 1149.1 (JTAG) Boundary Scan Support
Cyclone II devices also use the JTAG port to monitor the logic operation
of the device with the SignalTap^® II embedded logic analyzer. Cyclone II
devices support the JTAG instructions shown in Table 3–1.
Table 3–1. Cyclone II JTAG Instructions (Part 1 of 2)
JTAG Instruction
SAMPLE/PRELOAD
EXTEST (1)
BYPASS
USERCODE
IDCODE
HIGHZ (1)
CLAMP (1)
ICR
instructions
PULSE_NCONFIG
Instruction Code
00 0000 0101
00 0000 1111
11 1111 1111
00 0000 0111
00 0000 0110
00 0000 1011
00 0000 1010
00 0000 0001
Description
Allows a snapshot of signals at the device pins to be captured and
examined during normal device operation, and permits an initial
data pattern to be output at the device pins. Also used by the
SignalTap II embedded logic analyzer.
Allows the external circuitry and board-level interconnects to be
tested by forcing a test pattern at the output pins and capturing test
results at the input pins.
Places the 1-bit bypass register between the TDI and TDO pins,
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation.
Selects the 32-bit USERCODE register and places it between the
TDI and TDO pins, allowing the USERCODE to be serially shifted
out of TDO.
Selects the IDCODE register and places it between TDI and TDO,
allowing the IDCODE to be serially shifted out of TDO.
Places the 1-bit bypass register between the TDI and TDO pins,
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation, while
tri-stating all of the I/O pins.
Places the 1-bit bypass register between the TDI and TDO pins,
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation while
holding I/O pins to a state defined by the data in the boundary-scan
register.
Used when configuring a Cyclone II device via the JTAG port with
a USB Blaster^™, ByteBlaster^™ II, MasterBlaster^™ or
ByteBlasterMV^™ download cable, or when using a Jam File or JBC
File via an embedded processor.
Emulates pulsing the nCONFIG pin low to trigger reconfiguration
even though the physical pin is unaffected.
3–2
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007