EP2C8Q208C6 Datasheet, PDF (68/168 Pages) Altera Corporation – Section I. Cyclone II Device Family Data Sheet

I/O Structure & Features
Cyclone II devices support driver impedance matching to the impedance
of the transmission line, typically 25 or 50 Ω. When used with the output
drivers, on-chip termination sets the output driver impedance to 25 or
50 Ω. Cyclone II devices also support I/O driver series termination
(R_S = 50 Ω) for SSTL-2 and SSTL-18. Table 2–19 lists the I/O standards that
support impedance matching and series termination.
Table 2–19. I/O Standards Supporting Series Termination Note (1)
I/O Standards
3.3-V LVTTL and LVCMOS
2.5-V LVTTL and LVCMOS
1.8-V LVTTL and LVCMOS
SSTL-2 class I
SSTL-18 class I
Target R_S (Ω)
25 (2)
50 (2)
50 (2)
50 (2)
50 (2)
V_CCIO (V)
3.3
2.5
1.8
2.5
1.8
Notes to Table 2–19:
(1) Supported conditions are V_CCIO = V_CCIO ±50 mV.
(2) These R_S values are nominal values. Actual impedance varies across process,
voltage, and temperature conditions.
1 The recommended frequency range of operation is pending
silicon characterization.
On-chip series termination can be supported on any I/O bank. V_CCIO and
V_REF must be compatible for all I/O pins in order to enable on-chip series
termination in a given I/O bank. I/O standards that support different R_S
values can reside in the same I/O bank as long as their V_CCIO and V_REF are
not conflicting.
1 When using on-chip series termination, programmable drive
strength is not available.
Impedance matching is implemented using the capabilities of the output
driver and is subject to a certain degree of variation, depending on the
process, voltage and temperature. The actual tolerance is pending silicon
characterization.
2–56
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007