EP2C8Q208C6 Datasheet, PDF (61/168 Pages) Altera Corporation – Section I. Cyclone II Device Family Data Sheet

Cyclone II Architecture
Programmable Drive Strength
The output buffer for each Cyclone II device I/O pin has a programmable
drive strength control for certain I/O standards. The LVTTL, LVCMOS,
SSTL-2 class I and II, SSTL-18 class I and II, HSTL-18 class I and II, and
HSTL-1.5 class I and II standards have several levels of drive strength that
you can control. Using minimum settings provides signal slew rate
control to reduce system noise and signal overshoot. Table 2–16 shows
the possible settings for the I/O standards with drive strength control.
Table 2–16. Programmable Drive Strength (Part 1 of 2) Note (1)
I/O Standard
LVTTL (3.3 V)
LVCMOS (3.3 V)
LVTTL/LVCMOS (2.5 V)
LVTTL/LVCMOS (1.8 V)
I_OH/I_OL Current Strength Setting (mA)
Top & Bottom I/O Pins
Side I/O Pins
4
4
8
8
12
12
16
16
20
20
24
24
4
4
8
8
12
12
16
20
24
4
4
8
8
12
16
2
2
4
4
6
6
8
8
10
10
12
12
Altera Corporation
February 2007
2–49
Cyclone II Device Handbook, Volume 1