EP2C8Q208C6 Datasheet, PDF (66/168 Pages) Altera Corporation – Section I. Cyclone II Device Family Data Sheet

I/O Structure & Features
The reduced swing differential signaling (RSDS) and mini-LVDS
standards are derivatives of the LVDS standard. The RSDS and
mini-LVDS I/O standards are similar in electrical characteristics to
LVDS, but have a smaller voltage swing and therefore provide increased
power benefits and reduced electromagnetic interference (EMI).
Cyclone II devices support the RSDS and mini-LVDS I/O standards at
data rates up to 311 Mbps at the transmitter.
A subset of pins in each I/O bank (on both rows and columns) support
the high-speed I/O interface. The dual-purpose LVDS pins require an
external-resistor network at the transmitter channels in addition to 100-Ω
termination resistors on receiver channels. These pins do not contain
dedicated serialization or deserialization circuitry. Therefore, internal
logic performs serialization and deserialization functions.
Cyclone II pin tables list the pins that support the high-speed I/O
interface. The number of LVDS channels supported in each device family
member is listed in Table 2–18.
Table 2–18. Cyclone II Device LVDS Channels (Part 1 of 2)
Device
EP2C5
EP2C8
EP2C15
EP2C20
EP2C35
EP2C50
Pin Count
144
208
256
144
208
256
256
484
240
256
484
484
672
484
672
Number of LVDS
Channels (1)
31 (35)
56 (60)
61 (65)
29 (33)
53 (57)
75 (79)
52 (60)
128 (136)
45 (53)
52 (60)
128 (136)
131 (139)
201 (209)
119 (127)
189 (197)
2–54
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007