EP2C8Q208C6 Datasheet, PDF (145/168 Pages) Altera Corporation – Section I. Cyclone II Device Family Data Sheet

DC Characteristics and Timing Specifications
Table 5–46. Maximum Output Clock Toggle Rate Derating Factors (Part 4 of 4)
Maximum Output Clock Toggle Rate Derating Factors (ps/pF)
I/O Standard
SSTL_2_CLASS_I
SSTL_18_CLASS_I
Drive
Column I/O Pins
Row I/O Pins
Dedicated Clock
Outputs
Strength
–6 –7 –8 –6 –7 –8 –6 –7 –8
Speed Speed Speed Speed Speed Speed Speed Speed Speed
Grade Grade Grade Grade Grade Grade Grade Grade Grade
OCT_50 67 69 70 25 42 60 25 42 60
_OHMS
OCT_50 30 33 36 47 49 51 47 49 51
_OHMS
High Speed I/O Timing Specifications
The timing analysis for LVDS, mini-LVDS, and RSDS is different
compared to other I/O standards because the data communication is
source-synchronous.
You should also consider board skew, cable skew, and clock jitter in your
calculation. This section provides details on the timing parameters for
high-speed I/O standards in Cyclone II devices.
Table 5–47 defines the parameters of the timing diagram shown in
Figure 5–3.
Table 5–47. High-Speed I/O Timing Definitions (Part 1 of 2)
Parameter
Symbol
Description
High-speed clock
f_{H S C K L K} High-speed receiver and transmitter input and output clock frequency.
Duty cycle
t_{D UT Y} Duty cycle on high-speed transmitter output clock.
High-speed I/O data rate HSIODR High-speed receiver and transmitter input and output data rate.
Time unit interval
TUI
TUI = 1/HSIODR.
Channel-to-channel skew TCCS
The timing difference between the fastest and slowest output edges,
including t_CO variation and clock skew. The clock is included in the
TCCS measurement.
TCCS = TUI – SW – (2 × RSKM)
Altera Corporation
February 2008
5–55
Cyclone II Device Handbook, Volume 1