EP2C8Q208C6 Datasheet, PDF (35/168 Pages) Altera Corporation – Section I. Cyclone II Device Family Data Sheet

Cyclone II Architecture
Global Clock Network Distribution
Cyclone II devices contains 16 global clock networks. The device uses
multiplexers with these clocks to form six-bit buses to drive column IOE
clocks, LAB row clocks, or row IOE clocks (see Figure 2–14). Another
multiplexer at the LAB level selects two of the six LAB row clocks to feed
the LE registers within the LAB.
Figure 2–14. Global Clock Network Multiplexers
Global Clock
Network
Column I/O Region
IO_CLK [5..0]
Clock [15 or 7..0]
LAB Row Clock
LABCLK[5..0]
Row I/O Region
IO_CLK [5..0]
LAB row clocks can feed LEs, M4K memory blocks, and embedded
multipliers. The LAB row clocks also extend to the row I/O clock regions.
IOE clocks are associated with row or column block regions. Only six
global clock resources feed to these row and column regions. Figure 2–15
shows the I/O clock regions.
Altera Corporation
February 2007
2–23
Cyclone II Device Handbook, Volume 1