EP2C8Q208C6 Datasheet, PDF (17/168 Pages) Altera Corporation – Section I. Cyclone II Device Family Data Sheet

Figure 2–3. LE in Normal Mode
Packed Register Input
sload
sclear
(LAB Wide) (LAB Wide)
Register chain
connection
Cyclone II Architecture
data1
data2
data3
cin (from cout
of previous LE)
data4
Four-Input
LUT
clock (LAB Wide)
ena (LAB Wide)
aclr (LAB Wide)
Q
D
ENA
CLRN
Row, Column, and
Direct Link Routing
Row, Column, and
Direct Link Routing
Local routing
Register Feedback
Register
chain output
Arithmetic Mode
The arithmetic mode is ideal for implementing adders, counters,
accumulators, and comparators. An LE in arithmetic mode implements a
2-bit full adder and basic carry chain (see Figure 2–4). LEs in arithmetic
mode can drive out registered and unregistered versions of the LUT
output. Register feedback and register packing are supported when LEs
are used in arithmetic mode.
Altera Corporation
February 2007
2–5
Cyclone II Device Handbook, Volume 1