EP2C8Q208C6 Datasheet, PDF (55/168 Pages) Altera Corporation – Section I. Cyclone II Device Family Data Sheet

Cyclone II Architecture
Figure 2–25. Cyclone II IOE in Bidirectional I/O Configuration
io_clk[5..0]
Column
or Row
Interconect
OE
clkout
ce_out
aclr/prn
Chip-Wide Reset
sclr/preset
OE Register
PRN
DQ
ENA
CLRN
Output Register
PRN
DQ
ENA
CLRN
Output
Pin Delay
Open-Drain Output
V_CCIO
Optional
PCI Clamp
V_CCIO
Programmable
Pull-Up
Resistor
data_in1
data_in0
clkin
ce_in
Input Register
PRN
DQ
ENA
CLRN
Input Pin to
Input Register Delay
or Input Pin to
Logic Array Delay
Bus Hold
Altera Corporation
February 2007
The Cyclone II device IOE includes programmable delays to ensure zero
hold times, minimize setup times, or increase clock to output times.
A path in which a pin directly drives a register may require a
programmable delay to ensure zero hold time, whereas a path in which a
pin drives a register through combinational logic may not require the
delay. Programmable delays decrease input-pin-to-logic-array and IOE
input register delays. The Quartus II Compiler can program these delays
to automatically minimize setup time while providing a zero hold time.
2–43
Cyclone II Device Handbook, Volume 1