EP2C8Q208C6 Datasheet, PDF (42/168 Pages) Altera Corporation – Section I. Cyclone II Device Family Data Sheet

Embedded Memory
Memory Modes
Table 2–7 summarizes the different memory modes supported by the
M4K memory blocks.
Table 2–7. M4K Memory Modes
Memory Mode
Description
Single-port memory
M4K blocks support single-port mode, used when
simultaneous reads and writes are not required.
Single-port memory supports non-simultaneous
reads and writes.
Simple dual-port memory
Simple dual-port memory supports a
simultaneous read and write.
Simple dual-port with mixed Simple dual-port memory mode with different
width
read and write port widths.
True dual-port memory
True dual-port mode supports any combination of
two-port operations: two reads, two writes, or one
read and one write at two different clock
frequencies.
True dual-port with mixed
width
True dual-port mode with different read and write
port widths.
Embedded shift register
M4K memory blocks are used to implement shift
registers. Data is written into each address
location at the falling edge of the clock and read
from the address at the rising edge of the clock.
ROM
The M4K memory blocks support ROM mode. A
MIF initializes the ROM contents of these blocks.
FIFO buffers
A single clock or dual clock FIFO may be
implemented in the M4K blocks. Simultaneous
read and write from an empty FIFO buffer is not
supported.
1 Embedded Memory can be inferred in your HDL code or
directly instantiated in the Quartus II software using the
MegaWizard^® Plug-in Manager Memory Compiler feature.
2–30
Cyclone II Device Handbook, Volume 1
Altera Corporation
February 2007