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EP2C8Q208C6 Datasheet, PDF (149/168 Pages) Altera Corporation – Section I. Cyclone II Device Family Data Sheet | |||
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DC Characteristics and Timing Specifications
Figure 5â5. RSDS Transmitter Clock to Data Relationship
Transmitter
Clock (5.88 ns)
Channel-to-Channel
Skew (1.68 ns)
At transmitter
tx_data[11..0]
Transmitter
Valid
Data
Transmitter
Valid
Data
At receiver
rx_data[11..0]
Valid
Valid
Data
Data
Total
Skew
tSU (2 ns)
tH (2 ns)
Table 5â49 shows the mini-LVDS transmitter timing budget for Cyclone II
devices at 311 Mbps. Cyclone II devices cannot receive mini-LVDS data
because the devices are intended for applications where they will be
driving display drivers. A maximum mini-LVDS data rate of 311 Mbps is
supported for Cyclone II devices using DDIO registers. Cyclone II
devices support mini-LVDS only in the commercial temperature range.
Table 5â49. Mini-LVDS Transmitter Timing Specification (Part 1 of 2)
Symbol Conditions
fH S C L K
Ã10
(input
Ã8
clock
frequency)
Ã7
Ã4
Ã2
Ã1
â6 Speed Grade
Min Typ Max
10 â 155.5
10 â 155.5
10 â 155.5
10 â 155.5
10 â 155.5
10 â 311
â7 Speed Grade
Min Typ Max
10
â 155.5
10
â 155.5
10
â 155.5
10
â 155.5
10
â 155.5
10
â 311
â8 Speed Grade
Min Typ Max
10
â 155.5
10
â 155.5
10
â 155.5
10
â 155.5
10
â 155.5
10
â 311
Unit
MHz
MHz
MHz
MHz
MHz
MHz
Altera Corporation
February 2008
5â59
Cyclone II Device Handbook, Volume 1
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