HC20K400 Datasheet, PDF (4/36 Pages) Altera Corporation – HardCopy APEX Device Family

HardCopy Series Handbook, Volume 1
High-density architecture:
■ 400,000 to 1.5 million typical gates (Table 7–1)
■ Up to 51,840 logic elements (LEs)
■ Up to 442,368 RAM bits that can be used without reducing available
logic
Table 7–1. HardCopy APEX Device Features Note (1)
Feature
Maximum system gates
Typical gates
LEs
ESBs
Maximum RAM bits
Phase-locked loops (PLLs)
Maximum macrocells
Maximum user I/O pins
HC20K400
1,052,000
400,000
16,640
104
212,992
4
1,664
488
HC20K600
1,537,000
600,000
24,320
152
311,296
4
2,432
588
HC20K1000
1,772,000
1,000,000
38,400
160
327,680
4
2,560
708
HC20K1500
2,392,000
1,500,000
51,840
216
442,368
4
3,456
808
Note to Table 7–1:
(1) The embedded IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan circuitry contributes up to
57,000 additional gates.
...and More
Features
Low-power operation:
■ 1.8-V supply voltage (Table 7–2)
■ MultiVolt I/O support for 1.8-, 2.5-, and 3.3-V interfaces
■ ESBs offering power-saving mode
Flexible clock management circuitry with up to four phase-locked loops
(PLLs):
■ Built-in low-skew clock tree
■ Up to eight global clock signals
■ ClockLock feature reducing clock delay and skew
■ ClockBoost feature providing clock multiplication and division
■ ClockShift feature providing clock phase and delay shifting
Powerful I/O features:
■ Compliant with peripheral component interconnect Special Interest
Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V
operation at 33 or 66 MHz and 32 or 64 bits
7–2
Altera Corporation
September 2008