HC20K400 Datasheet, PDF (17/36 Pages) Altera Corporation – HardCopy APEX Device Family

9. Boundary-Scan Support
H51009-2.3
IEEE Std. 1149.1
(JTAG)
Boundary-Scan
Support
All HardCopy devices provide JTAG boundary-scan test (BST) circuitry
that complies with the IEEE Std. 1149.1-1990 specification. HardCopy^®
APEX™ devices support the JTAG instructions shown in Table 9–1.
1 The BSDL files for HardCopy devices are different from the
corresponding APEX 20KE or APEX 20KC parts. Download the
correct HardCopy BSDL file from Altera’s website at
www.altera.com.
Table 9–1. HardCopy APEX JTAG Instructions
JTAG Instruction
SAMPLE/PRELOAD
EXTEST
BYPASS
USERCODE
IDCODE
Description
SAMPLE/PRELOAD allows a snapshot of signals at the device pins to be
captured and examined during normal device operation and permits an initial
data pattern to be output at the device pins. It is also used by the SignalTap^®
embedded logic analyzer.
Allows the external circuitry and board-level interconnections to be tested by
forcing a test pattern at the output pins and capturing test results at the input pins.
Places the 1-bit bypass register between the TDI and TDO pins, which allows the
BST data to pass synchronously through selected devices to adjacent devices
during normal device operation.
Selects the 32-bit USERCODE register and places it between the TDI and TDO
pins, allowing the USERCODE to be serially shifted out of TDO.
Selects the IDCODE register and places it between the TDI and TDO pins,
allowing the IDCODE to be serially shifted out of TDO.
HardCopy APEX devices instruction register length is 10 bits; the
USERCODE register length is 32 bits. Tables 9–2 and 9–3 show the
boundary-scan register length and device IDCODE information for
HardCopy devices.
Altera Corporation
9–1
September 2008